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| author | Schuyler Eldridge | 2019-08-07 18:00:29 -0400 |
|---|---|---|
| committer | Schuyler Eldridge | 2019-08-08 15:19:33 -0400 |
| commit | 9e99adbe920f3127e02a8dac05c972e3ea518c12 (patch) | |
| tree | 8c37e85d17ed616df9bb454b7dd39e5b3bd14922 /chiselFrontend/src/main | |
| parent | 59d72b37d38556b7d11e55c44057d01e07fe1e31 (diff) | |
Require target is hardware for Vec.apply(a: UInt)
Adds a check that a Vec being indexed by a UInt is, in fact, a
hardware type. This includes a test for this.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Diffstat (limited to 'chiselFrontend/src/main')
| -rw-r--r-- | chiselFrontend/src/main/scala/chisel3/Aggregate.scala | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/chiselFrontend/src/main/scala/chisel3/Aggregate.scala b/chiselFrontend/src/main/scala/chisel3/Aggregate.scala index 9149447a..dfba1caf 100644 --- a/chiselFrontend/src/main/scala/chisel3/Aggregate.scala +++ b/chiselFrontend/src/main/scala/chisel3/Aggregate.scala @@ -216,6 +216,7 @@ sealed class Vec[T <: Data] private[chisel3] (gen: => T, val length: Int) /** @group SourceInfoTransformMacro */ def do_apply(p: UInt)(implicit compileOptions: CompileOptions): T = { + requireIsHardware(this, "vec") requireIsHardware(p, "vec index") val port = gen |