summaryrefslogtreecommitdiff
path: root/chiselFrontend/src/main
diff options
context:
space:
mode:
authorJack Koenig2019-12-02 16:06:16 -0800
committerGitHub2019-12-02 16:06:16 -0800
commit8edca94f94dac5e8b9a6a8793e88a7782d351401 (patch)
tree7c303daf185e21b692488b856a4d2c8b7c990457 /chiselFrontend/src/main
parentf13cedbe28078cfa2d3fa4c196967b0e8a251c80 (diff)
Fix asTypeOf for Clock (#1258)
Diffstat (limited to 'chiselFrontend/src/main')
-rw-r--r--chiselFrontend/src/main/scala/chisel3/Clock.scala2
1 files changed, 1 insertions, 1 deletions
diff --git a/chiselFrontend/src/main/scala/chisel3/Clock.scala b/chiselFrontend/src/main/scala/chisel3/Clock.scala
index 7e530cdf..87674e7b 100644
--- a/chiselFrontend/src/main/scala/chisel3/Clock.scala
+++ b/chiselFrontend/src/main/scala/chisel3/Clock.scala
@@ -33,6 +33,6 @@ sealed class Clock(private[chisel3] val width: Width = Width(1)) extends Element
override def do_asUInt(implicit sourceInfo: SourceInfo, connectCompileOptions: CompileOptions): UInt = pushOp(DefPrim(sourceInfo, UInt(this.width), AsUIntOp, ref)) // scalastyle:ignore line.size.limit
private[chisel3] override def connectFromBits(that: Bits)(implicit sourceInfo: SourceInfo,
compileOptions: CompileOptions): Unit = {
- this := that
+ this := that.asBool.asClock
}
}