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authorSchuyler Eldridge2018-10-28 11:30:45 -0400
committerGitHub2018-10-28 11:30:45 -0400
commit44124f2ec92cf24814a8343ae3faef9abe916626 (patch)
tree3af980704f34346d4e983348a269885ffe6a8910 /chiselFrontend/src/main
parent600405254c20c14fb3389aa4758ec27dffe992d0 (diff)
parentf64388e7cfe71004df93ddeef88447978f37ecb1 (diff)
Merge pull request #912 from seldridge/c911
Make BaseModule.name lazy
Diffstat (limited to 'chiselFrontend/src/main')
-rw-r--r--chiselFrontend/src/main/scala/chisel3/core/Module.scala8
1 files changed, 7 insertions, 1 deletions
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Module.scala b/chiselFrontend/src/main/scala/chisel3/core/Module.scala
index 88013bae..3bdc86d6 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Module.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Module.scala
@@ -180,7 +180,13 @@ abstract class BaseModule extends HasId {
def desiredName = this.getClass.getName.split('.').last
/** Legalized name of this module. */
- final val name = Builder.globalNamespace.name(desiredName)
+ final lazy val name = try {
+ Builder.globalNamespace.name(desiredName)
+ } catch {
+ case e: NullPointerException => throwException(
+ s"Error: desiredName of ${this.getClass.getName} is null. Did you evaluate 'name' before all values needed by desiredName were available?", e)
+ case t: Throwable => throw t
+ }
/** Returns a FIRRTL ModuleName that references this object
* @note Should not be called until circuit elaboration is complete