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| author | Stephen Twigg | 2016-04-26 19:39:18 -0700 |
|---|---|---|
| committer | Andrew Waterman | 2016-05-04 01:35:59 -0700 |
| commit | 24492361da393a5b4d3e023b6511693125f4f254 (patch) | |
| tree | 11677918e6d952c0ed752a3bd40c52b64cc5aa43 /chiselFrontend/src/main | |
| parent | 73e35c55c7a3f4be98432fd275e0e0ae7db76d46 (diff) | |
Rewrite BlackBox IO contract, replace _clock|_reset
The old blackbox behavior still emitted extmodules that have a
clk, reset pin and prepended all io's with io_ (ultimately). Most
verilog modules do not follow this distinction (or use a slightly
different name for clock and so on).
Thus, instead BlackBox has been rewritten to not assume a clk or
reset pin. Instead, the io Bundle specified is flattened directly
into the Module.ports declaration. The tests have been rewritten
to compensate for this. Also, added a test that uses the clock pin.
As a secondary change, the _clock and _reset module parameters were
bad for two reasons. One, they used null as a default, which is a
scala best practices violation. Two, they were just not good names.
Instead the primary constructor has been rewritten to take an
Option[Clock] called override_clock and an Option[Bool] called
override_reset, which default to None. (Note how the getOrElse call
down below is much more natural now.)
However, users may not want to specify the Some(their_clock) so I
also added secondary constructors that take parameters named clock
and reset and wrap them into Some calls into the primary constructor.
This is a better UX because now you can just stipulate clock=blah in
instantiation of that module in symmetry with using the clock in the
definition of the module by invoking clock.
PS: We could also back out of allowing any overrides via the Module
constructor and just require the instantiating Module to do
submodule.clock := newclock, etc.
Diffstat (limited to 'chiselFrontend/src/main')
0 files changed, 0 insertions, 0 deletions
