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authorRichard Lin2019-03-21 15:57:32 -0700
committerGitHub2019-03-21 15:57:32 -0700
commit1183e98cfd0626f879177f693682c917f28e3d62 (patch)
treea1e60e338e096a9b72cb14139a1e845062f5cfc9 /chiselFrontend/src/main
parent5f8344cb2ef3571a1fe01e8a2b6827fa4ff1b2e0 (diff)
Change == to reference equality (eq) in Data print (#1044)
Diffstat (limited to 'chiselFrontend/src/main')
-rw-r--r--chiselFrontend/src/main/scala/chisel3/core/Data.scala2
1 files changed, 1 insertions, 1 deletions
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Data.scala b/chiselFrontend/src/main/scala/chisel3/core/Data.scala
index 45afed94..64c84c05 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Data.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Data.scala
@@ -314,7 +314,7 @@ abstract class Data extends HasId with NamedComponent with SourceInfoDoc { // sc
case Some(MemoryPortBinding(enclosure)) => s"(MemPort in ${enclosure.desiredName})"
case Some(PortBinding(enclosure)) if !enclosure.isClosed => s"(IO in unelaborated ${enclosure.desiredName})"
case Some(PortBinding(enclosure)) if enclosure.isClosed =>
- DataMirror.fullModulePorts(enclosure).find(_._2 == this) match {
+ DataMirror.fullModulePorts(enclosure).find(_._2 eq this) match {
case Some((name, _)) => s"(IO $name in ${enclosure.desiredName})"
case None => s"(IO (unknown) in ${enclosure.desiredName})"
}