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authorChick Markley2016-08-26 08:19:51 -0700
committerGitHub2016-08-26 08:19:51 -0700
commit0c34480c5049c000e03b7b1a174e4bd6cca682cb (patch)
treea3ea3175792b9a1424179b02359966c6d8531b1d /chiselFrontend/src/main
parentddb7278760029be9d960ba8bf2b06ac8a8aac767 (diff)
parent5ca2820216a4c4b8c28438967d6e4680412f6580 (diff)
Merge pull request #259 from ucb-bar/addpublicnode
Public APIs for chisel object names
Diffstat (limited to 'chiselFrontend/src/main')
-rw-r--r--chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala2
-rw-r--r--chiselFrontend/src/main/scala/chisel3/core/Module.scala23
-rw-r--r--chiselFrontend/src/main/scala/chisel3/internal/Builder.scala34
3 files changed, 56 insertions, 3 deletions
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala b/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala
index 15643ac8..82c6097f 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala
@@ -374,5 +374,5 @@ class Bundle extends Aggregate(NO_DIR) {
private[core] object Bundle {
val keywords = List("flip", "asInput", "asOutput", "cloneType", "toBits",
- "widthOption")
+ "widthOption", "signalName", "signalPathName", "signalParent", "signalComponent")
}
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Module.scala b/chiselFrontend/src/main/scala/chisel3/core/Module.scala
index 5af744c4..2426ae78 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Module.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Module.scala
@@ -31,7 +31,9 @@ object Module {
m._commands.prepend(DefInvalid(childSourceInfo, m.io.ref)) // init module outputs
dynamicContext.currentModule = parent
val ports = m.computePorts
- Builder.components += Component(m, m.name, ports, m._commands)
+ val component = Component(m, m.name, ports, m._commands)
+ m._component = Some(component)
+ Builder.components += component
pushCommand(DefInstance(sourceInfo, m, ports))
m.setupInParent(childSourceInfo)
}
@@ -63,6 +65,25 @@ extends HasId {
/** Legalized name of this module. */
final val name = Builder.globalNamespace.name(desiredName)
+ /** FIRRTL Module name */
+ private var _modName: Option[String] = None
+ private[chisel3] def setModName(name: String) = _modName = Some(name)
+ def modName = _modName match {
+ case Some(name) => name
+ case None => throwException("modName should be called after circuit elaboration")
+ }
+
+ /** Keep component for signal names */
+ private[chisel3] var _component: Option[Component] = None
+
+
+ /** Signal name (for simulation). */
+ override def instanceName =
+ if (_parent == None) name else _component match {
+ case None => getRef.name
+ case Some(c) => getRef fullName c
+ }
+
/** IO for this Module. At the Scala level (pre-FIRRTL transformations),
* connections in and out of a Module may only go through `io` elements.
*/
diff --git a/chiselFrontend/src/main/scala/chisel3/internal/Builder.scala b/chiselFrontend/src/main/scala/chisel3/internal/Builder.scala
index cecbd91e..2dec78bb 100644
--- a/chiselFrontend/src/main/scala/chisel3/internal/Builder.scala
+++ b/chiselFrontend/src/main/scala/chisel3/internal/Builder.scala
@@ -55,7 +55,18 @@ private[chisel3] class IdGen {
}
}
-private[chisel3] trait HasId {
+/** Public API to access Node/Signal names.
+ * currently, the node's name, the full path name, and references to its parent Module and component.
+ * These are only valid once the design has been elaborated, and should not be used during its construction.
+ */
+trait InstanceId {
+ def instanceName: String
+ def pathName: String
+ def parentPathName: String
+ def parentModName: String
+}
+
+private[chisel3] trait HasId extends InstanceId {
private[chisel3] def _onModuleClose {} // scalastyle:ignore method.name
private[chisel3] val _parent = Builder.dynamicContext.currentModule
_parent.foreach(_.addId(this))
@@ -95,6 +106,27 @@ private[chisel3] trait HasId {
private[chisel3] def setRef(parent: HasId, index: Int): Unit = setRef(Index(Node(parent), ILit(index)))
private[chisel3] def setRef(parent: HasId, index: UInt): Unit = setRef(Index(Node(parent), index.ref))
private[chisel3] def getRef: Arg = _ref.get
+
+ // Implementation of public methods.
+ def instanceName = _parent match {
+ case Some(p) => p._component match {
+ case Some(c) => getRef fullName c
+ case None => throwException("signalName/pathName should be called after circuit elaboration")
+ }
+ case None => throwException("this cannot happen")
+ }
+ def pathName = _parent match {
+ case None => instanceName
+ case Some(p) => s"${p.pathName}.$instanceName"
+ }
+ def parentPathName = _parent match {
+ case Some(p) => p.pathName
+ case None => throwException(s"$instanceName doesn't have a parent")
+ }
+ def parentModName = _parent match {
+ case Some(p) => p.modName
+ case None => throwException(s"$instanceName doesn't have a parent")
+ }
}
private[chisel3] class DynamicContext {