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| author | Schuyler Eldridge | 2019-03-15 14:15:32 -0600 |
|---|---|---|
| committer | edwardcwang | 2019-03-15 13:15:32 -0700 |
| commit | c275d64712c1aee8d81f6b6505333f577d075bf6 (patch) | |
| tree | f13f069fbaddf921a53bb752b433a026319aec39 /chiselFrontend/src/main/scala | |
| parent | 9120df2fac77b2ba7f0372e2ff9ad7f321d66978 (diff) | |
Use TransitName for improved Pipe naming (#1024)
This changes from using the chiselname annotation on Pipe.apply to
using an explicit TransitName. This results in an improved name for
created valid and bits registers.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Diffstat (limited to 'chiselFrontend/src/main/scala')
0 files changed, 0 insertions, 0 deletions