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authorJim Lawson2020-01-07 14:35:18 -0800
committerGitHub2020-01-07 14:35:18 -0800
commitc4aa70f64ad5ecd8a5557ad0e4777f245768d865 (patch)
treea447f56b55065bdc2f4e05e0195f050e2cb431db /chiselFrontend/src/main/scala/chisel3/internal
parent2224274cc5a42caa1e74b45573b4c7c09c85d227 (diff)
parentd4300b9deae6dde7ce0f314ea73a9ca4a1c3868c (diff)
Merge branch 'master' into add-asbool-to-clock
Diffstat (limited to 'chiselFrontend/src/main/scala/chisel3/internal')
-rw-r--r--chiselFrontend/src/main/scala/chisel3/internal/Builder.scala2
1 files changed, 1 insertions, 1 deletions
diff --git a/chiselFrontend/src/main/scala/chisel3/internal/Builder.scala b/chiselFrontend/src/main/scala/chisel3/internal/Builder.scala
index b5f617f0..c119315d 100644
--- a/chiselFrontend/src/main/scala/chisel3/internal/Builder.scala
+++ b/chiselFrontend/src/main/scala/chisel3/internal/Builder.scala
@@ -18,7 +18,7 @@ private[chisel3] class Namespace(keywords: Set[String]) {
names(keyword) = 1
private def rename(n: String): String = {
- val index = names.getOrElse(n, 1L)
+ val index = names(n)
val tryName = s"${n}_${index}"
names(n) = index + 1
if (this contains tryName) rename(n) else tryName