diff options
| author | Richard Lin | 2019-07-18 22:39:27 -0700 |
|---|---|---|
| committer | GitHub | 2019-07-18 22:39:27 -0700 |
| commit | aaf963f95bf1f4e9f3e5a8225925b4df7d01e795 (patch) | |
| tree | 1121b2fbdcb8a22e23524e73c3211bd01df6a135 /chiselFrontend/src/main/scala/chisel3/internal/BiConnect.scala | |
| parent | ae784b6e9dde1a5692b37067573cfddc164cdf26 (diff) | |
Support Analog DontCare bulk-connect (#1056)
Short-term patch to enable this useful behavior. In the future, we may want to rearchitect the type system and/or rethink the more edge-case connect behavior.
Diffstat (limited to 'chiselFrontend/src/main/scala/chisel3/internal/BiConnect.scala')
| -rw-r--r-- | chiselFrontend/src/main/scala/chisel3/internal/BiConnect.scala | 35 |
1 files changed, 18 insertions, 17 deletions
diff --git a/chiselFrontend/src/main/scala/chisel3/internal/BiConnect.scala b/chiselFrontend/src/main/scala/chisel3/internal/BiConnect.scala index e122f13a..f49deff4 100644 --- a/chiselFrontend/src/main/scala/chisel3/internal/BiConnect.scala +++ b/chiselFrontend/src/main/scala/chisel3/internal/BiConnect.scala @@ -61,11 +61,20 @@ private[chisel3] object BiConnect { // Handle element case (root case) case (left_a: Analog, right_a: Analog) => try { - analogAttach(sourceInfo, left_a, right_a, context_mod) - } catch { - // If attach fails, convert to BiConnectException + markAnalogConnected(sourceInfo, left_a, context_mod) + markAnalogConnected(sourceInfo, right_a, context_mod) + } catch { // convert attach exceptions to BiConnectExceptions case attach.AttachException(message) => throw BiConnectException(message) } + attach.impl(Seq(left_a, right_a), context_mod)(sourceInfo) + case (left_a: Analog, DontCare) => + try { + markAnalogConnected(sourceInfo, left_a, context_mod) + } catch { // convert attach exceptions to BiConnectExceptions + case attach.AttachException(message) => throw BiConnectException(message) + } + pushCommand(DefInvalid(sourceInfo, left_a.lref)) + case (DontCare, right_a: Analog) => connect(sourceInfo, connectCompileOptions, right, left, context_mod) case (left_e: Element, right_e: Element) => { elemConnect(sourceInfo, connectCompileOptions, left_e, right_e, context_mod) // TODO(twigg): Verify the element-level classes are connectable @@ -312,21 +321,13 @@ private[chisel3] object BiConnect { else throw UnknownRelationException } - // This function checks if analog element-level attaching is allowed - // Then it either issues it or throws the appropriate exception. - def analogAttach(implicit sourceInfo: SourceInfo, left: Analog, right: Analog, contextModule: RawModule): Unit = { - // Error if left or right is BICONNECTED in the current module already - for (elt <- left :: right :: Nil) { - elt.biConnectLocs.get(contextModule) match { - case Some(sl) => throw AttachAlreadyBulkConnectedException(sl) - case None => // Do nothing - } + // This function checks if analog element-level attaching is allowed, then marks the Analog as connected + def markAnalogConnected(implicit sourceInfo: SourceInfo, analog: Analog, contextModule: RawModule): Unit = { + analog.biConnectLocs.get(contextModule) match { + case Some(sl) => throw AttachAlreadyBulkConnectedException(sl) + case None => // Do nothing } - - // Do the attachment - attach.impl(Seq(left, right), contextModule) // Mark bulk connected - left.biConnectLocs(contextModule) = sourceInfo - right.biConnectLocs(contextModule) = sourceInfo + analog.biConnectLocs(contextModule) = sourceInfo } } |
