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authorJack Koenig2017-02-09 16:17:18 -0800
committerAndrew Waterman2017-02-24 17:39:58 -0800
commitd7d658d856f47e0b82ad99120631536f7652bf09 (patch)
treeb7343b5a2e83a818fbd36aed519aa13751bcabda /chiselFrontend/src/main/scala/chisel3/core
parentab083035655cbe1b1d73fc1d36db08cce8811fec (diff)
Fix mismatch between Chisel and Firrtl on UInt -& UInt
Fixes #501. Also added UIntOps test.
Diffstat (limited to 'chiselFrontend/src/main/scala/chisel3/core')
-rw-r--r--chiselFrontend/src/main/scala/chisel3/core/Bits.scala2
1 files changed, 1 insertions, 1 deletions
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Bits.scala b/chiselFrontend/src/main/scala/chisel3/core/Bits.scala
index 574184d1..fccc6f08 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Bits.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Bits.scala
@@ -436,7 +436,7 @@ sealed class UInt private[core] (width: Width, lit: Option[ULit] = None)
def do_+% (that: UInt)(implicit sourceInfo: SourceInfo): UInt =
(this +& that).tail(1)
def do_-& (that: UInt)(implicit sourceInfo: SourceInfo): UInt =
- binop(sourceInfo, UInt((this.width max that.width) + 1), SubOp, that)
+ binop(sourceInfo, SInt((this.width max that.width) + 1), SubOp, that).asUInt
def do_-% (that: UInt)(implicit sourceInfo: SourceInfo): UInt =
(this -& that).tail(1)