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| author | Adam Izraelevitz | 2017-09-06 13:24:20 -0700 |
|---|---|---|
| committer | GitHub | 2017-09-06 13:24:20 -0700 |
| commit | a97fbfca90ba1a2604c89d3595a49d5260bd5f91 (patch) | |
| tree | 8655572083aaf26200e95d9982ef26b6b78dde55 /chiselFrontend/src/main/scala/chisel3/core | |
| parent | 1be90a1e04383675f5b6d967872904ee3dd55faf (diff) | |
Added API to get Verilog from Chisel (#676)
* Added API to get Verilog from Chisel
* Removed second emitVerilog implementation, added scaladoc
Diffstat (limited to 'chiselFrontend/src/main/scala/chisel3/core')
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