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| author | chick | 2016-08-18 13:03:16 -0700 |
|---|---|---|
| committer | Donggyu Kim | 2016-08-21 22:30:10 -0700 |
| commit | 3f771ee67b9f8fa0d92ce00af1ea062c5a2605b2 (patch) | |
| tree | ca449c73092eab6d094d87751e3cff1cb3802939 /chiselFrontend/src/main/scala/chisel3/core | |
| parent | bc4f64020b8115d04af00e92bf9a7c68d9b35443 (diff) | |
Add AnnotationSpec file which provides an example of a way to implement generation of annotations in a chisel circuit that could be used by custom firrtl passes
This spec also shows and tests in a limited way the new API of .signalName, .pathName, parentModName which allows access to the various path information of a chisel component (something that subclasses SignalId, most prominently SubClasses of Data and Module
Diffstat (limited to 'chiselFrontend/src/main/scala/chisel3/core')
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