diff options
| author | Jack Koenig | 2018-11-21 15:34:42 -0800 |
|---|---|---|
| committer | Jack Koenig | 2018-12-04 13:13:13 -0800 |
| commit | 3db21bd8e5a32c29efa55494d180dac4d22589e5 (patch) | |
| tree | c21edf9bc9c5f2f42ec5716a829145024bb82862 /chiselFrontend/src/main/scala/chisel3/core | |
| parent | 121635ed26c8a9852c827d6c0729515337604d08 (diff) | |
Add asBool, deprecate toBool
Diffstat (limited to 'chiselFrontend/src/main/scala/chisel3/core')
| -rw-r--r-- | chiselFrontend/src/main/scala/chisel3/core/Assert.scala | 4 | ||||
| -rw-r--r-- | chiselFrontend/src/main/scala/chisel3/core/Bits.scala | 17 | ||||
| -rw-r--r-- | chiselFrontend/src/main/scala/chisel3/core/Printf.scala | 2 |
3 files changed, 18 insertions, 5 deletions
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Assert.scala b/chiselFrontend/src/main/scala/chisel3/core/Assert.scala index 92f602c4..77db3692 100644 --- a/chiselFrontend/src/main/scala/chisel3/core/Assert.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/Assert.scala @@ -53,7 +53,7 @@ object assert { // scalastyle:ignore object.name def apply_impl_do(cond: Bool, line: String, message: Option[String], data: Bits*)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions) { val escLine = line.replaceAll("%", "%%") - when (!(cond || Module.reset.toBool)) { + when (!(cond || Module.reset.asBool)) { val fmt = message match { case Some(msg) => s"Assertion failed: $msg\n at $escLine\n" @@ -80,7 +80,7 @@ object assert { // scalastyle:ignore object.name object stop { // scalastyle:ignore object.name /** Terminate execution with a failure code. */ def apply(code: Int)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Unit = { - when (!Module.reset.toBool) { + when (!Module.reset.asBool) { pushCommand(Stop(sourceInfo, Builder.forcedClock.ref, code)) } } diff --git a/chiselFrontend/src/main/scala/chisel3/core/Bits.scala b/chiselFrontend/src/main/scala/chisel3/core/Bits.scala index b7c303f0..7e98cf04 100644 --- a/chiselFrontend/src/main/scala/chisel3/core/Bits.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/Bits.scala @@ -82,6 +82,15 @@ private[chisel3] sealed trait ToBoolable extends Element { * * @note The width must be known and equal to 1 */ + final def asBool(): Bool = macro SourceInfoWhiteboxTransform.noArg + + /** @group SourceInfoTransformMacro */ + def do_asBool(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bool + + /** Casts this $coll to a [[Bool]] + * + * @note The width must be known and equal to 1 + */ final def toBool(): Bool = macro SourceInfoWhiteboxTransform.noArg /** @group SourceInfoTransformMacro */ @@ -420,13 +429,17 @@ sealed abstract class Bits(private[chisel3] val width: Width) extends Element wi do_asUInt } - final def do_toBool(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bool = { + final def do_asBool(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bool = { width match { case KnownWidth(1) => this(0) - case _ => throwException(s"can't covert UInt<$width> to Bool") + case _ => throwException(s"can't covert ${this.getClass.getSimpleName}$width to Bool") } } + @chiselRuntimeDeprecated + @deprecated("Use asBool instead", "3.2") + final def do_toBool(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bool = do_asBool + /** Concatenation operator * * @param that a hardware component diff --git a/chiselFrontend/src/main/scala/chisel3/core/Printf.scala b/chiselFrontend/src/main/scala/chisel3/core/Printf.scala index bfab57d8..53b62bc8 100644 --- a/chiselFrontend/src/main/scala/chisel3/core/Printf.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/Printf.scala @@ -86,7 +86,7 @@ object printf { // scalastyle:ignore object.name * @param pable [[Printable]] to print */ def apply(pable: Printable)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Unit = { - when (!Module.reset.toBool) { + when (!Module.reset.asBool) { printfWithoutReset(pable) } } |
