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authorRichard Lin2016-11-21 13:44:26 -0800
committerGitHub2016-11-21 13:44:26 -0800
commit3b4755716a74d4711efa3ce6799742479e17e80b (patch)
tree56652eaa478d5dfd8cddfbe2795c0123d39d230d /chiselFrontend/src/main/scala/chisel3/core
parentcd6eb41275381a4399a8a88c886110d276bb805c (diff)
parent81e5d00d18a5ba9ae33c10219a270148002fc672 (diff)
Merge pull request #372 from ucb-bar/onetrueliteral
Standardize the One True Way of specifying literals
Diffstat (limited to 'chiselFrontend/src/main/scala/chisel3/core')
-rw-r--r--chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala14
-rw-r--r--chiselFrontend/src/main/scala/chisel3/core/Bits.scala158
-rw-r--r--chiselFrontend/src/main/scala/chisel3/core/Mem.scala2
-rw-r--r--chiselFrontend/src/main/scala/chisel3/core/SeqUtils.scala6
-rw-r--r--chiselFrontend/src/main/scala/chisel3/core/When.scala4
-rw-r--r--chiselFrontend/src/main/scala/chisel3/core/package.scala106
6 files changed, 151 insertions, 139 deletions
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala b/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala
index de7af462..8fdcb260 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala
@@ -123,10 +123,10 @@ object Vec {
/** Truncate an index to implement modulo-power-of-2 addressing. */
private[core] def truncateIndex(idx: UInt, n: Int)(implicit sourceInfo: SourceInfo): UInt = {
val w = BigInt(n-1).bitLength
- if (n <= 1) UInt(0)
+ if (n <= 1) 0.U
else if (idx.width.known && idx.width.get <= w) idx
else if (idx.width.known) idx(w-1,0)
- else (idx | UInt(0, w))(w-1,0)
+ else (idx | 0.U(w))(w-1,0)
}
}
@@ -249,7 +249,7 @@ trait VecLike[T <: Data] extends collection.IndexedSeq[T] with HasId {
// IndexedSeq has its own hashCode/equals that we must not use
override def hashCode: Int = super[HasId].hashCode
override def equals(that: Any): Boolean = super[HasId].equals(that)
-
+
@deprecated("Use Vec.apply instead", "chisel3")
def read(idx: UInt): T
@@ -261,14 +261,14 @@ trait VecLike[T <: Data] extends collection.IndexedSeq[T] with HasId {
def forall(p: T => Bool): Bool = macro SourceInfoTransform.pArg
def do_forall(p: T => Bool)(implicit sourceInfo: SourceInfo): Bool =
- (this map p).fold(Bool(true))(_ && _)
+ (this map p).fold(true.B)(_ && _)
/** Outputs true if p outputs true for at least one element.
*/
def exists(p: T => Bool): Bool = macro SourceInfoTransform.pArg
def do_exists(p: T => Bool)(implicit sourceInfo: SourceInfo): Bool =
- (this map p).fold(Bool(false))(_ || _)
+ (this map p).fold(false.B)(_ || _)
/** Outputs true if the vector contains at least one element equal to x (using
* the === operator).
@@ -288,7 +288,7 @@ trait VecLike[T <: Data] extends collection.IndexedSeq[T] with HasId {
/** Helper function that appends an index (literal value) to each element,
* useful for hardware generators which output an index.
*/
- private def indexWhereHelper(p: T => Bool) = this map p zip (0 until length).map(i => UInt(i))
+ private def indexWhereHelper(p: T => Bool) = this map p zip (0 until length).map(i => i.asUInt)
/** Outputs the index of the first element for which p outputs true.
*/
@@ -388,7 +388,7 @@ class Bundle extends Aggregate {
private[chisel3] lazy val flatten = namedElts.flatMap(_._2.flatten)
private[chisel3] override def _onModuleClose: Unit = // scalastyle:ignore method.name
for ((name, elt) <- namedElts) { elt.setRef(this, _namespace.name(name)) }
-
+
private[chisel3] final def allElements: Seq[Element] = namedElts.flatMap(_._2.allElements)
override def cloneType : this.type = {
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Bits.scala b/chiselFrontend/src/main/scala/chisel3/core/Bits.scala
index 82b60a4c..354512e1 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Bits.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Bits.scala
@@ -92,7 +92,7 @@ sealed abstract class Bits(width: Width, override val litArg: Option[LitArg])
Builder.error(s"Negative bit indices are illegal (got $x)")
}
if (isLit()) {
- Bool(((litValue() >> x.toInt) & 1) == 1)
+ (((litValue() >> x.toInt) & 1) == 1).asBool
} else {
Binding.checkSynthesizable(this, s"'this' ($this)")
pushOp(DefPrim(sourceInfo, Bool(), BitsExtractOp, this.ref, ILit(x), ILit(x)))
@@ -134,7 +134,7 @@ sealed abstract class Bits(width: Width, override val litArg: Option[LitArg])
}
val w = x - y + 1
if (isLit()) {
- UInt((litValue >> y) & ((BigInt(1) << w) - 1), w)
+ ((litValue >> y) & ((BigInt(1) << w) - 1)).asUInt(w.W)
} else {
Binding.checkSynthesizable(this, s"'this' ($this)")
pushOp(DefPrim(sourceInfo, UInt(Width(w)), BitsExtractOp, this.ref, ILit(x), ILit(y)))
@@ -304,11 +304,6 @@ sealed abstract class Bits(width: Width, override val litArg: Option[LitArg])
final def toPrintable: Printable = Decimal(this)
}
-/** Provides a set of operations to create UInt types and literals.
- * Identical in functionality to the UInt companion object.
- */
-object Bits extends UIntFactory
-
// REVIEW TODO: Further discussion needed on what Num actually is.
/** Abstract trait defining operations available on numeric-like wire data
* types.
@@ -408,14 +403,14 @@ sealed class UInt private[core] (width: Width, lit: Option[ULit] = None)
private[chisel3] def toType = s"UInt$width"
override private[chisel3] def fromInt(value: BigInt, width: Int): this.type =
- UInt(value, width).asInstanceOf[this.type]
+ value.asUInt(width.W).asInstanceOf[this.type]
// TODO: refactor to share documentation with Num or add independent scaladoc
final def unary_- (): UInt = macro SourceInfoTransform.noArg
final def unary_-% (): UInt = macro SourceInfoTransform.noArg
- def do_unary_- (implicit sourceInfo: SourceInfo) : UInt = UInt(0) - this
- def do_unary_-% (implicit sourceInfo: SourceInfo): UInt = UInt(0) -% this
+ def do_unary_- (implicit sourceInfo: SourceInfo) : UInt = 0.U - this
+ def do_unary_-% (implicit sourceInfo: SourceInfo): UInt = 0.U -% this
override def do_+ (that: UInt)(implicit sourceInfo: SourceInfo): UInt = this +% that
override def do_- (that: UInt)(implicit sourceInfo: SourceInfo): UInt = this -% that
@@ -463,8 +458,8 @@ sealed class UInt private[core] (width: Width, lit: Option[ULit] = None)
final def andR(): Bool = macro SourceInfoTransform.noArg
final def xorR(): Bool = macro SourceInfoTransform.noArg
- def do_orR(implicit sourceInfo: SourceInfo): Bool = this != UInt(0)
- def do_andR(implicit sourceInfo: SourceInfo): Bool = ~this === UInt(0)
+ def do_orR(implicit sourceInfo: SourceInfo): Bool = this != 0.U
+ def do_andR(implicit sourceInfo: SourceInfo): Bool = ~this === 0.U
def do_xorR(implicit sourceInfo: SourceInfo): Bool = redop(sourceInfo, XorReduceOp)
override def do_< (that: UInt)(implicit sourceInfo: SourceInfo): Bool = compop(sourceInfo, LessOp, that)
@@ -483,7 +478,7 @@ sealed class UInt private[core] (width: Width, lit: Option[ULit] = None)
final def unary_! () : Bool = macro SourceInfoTransform.noArg
- def do_unary_! (implicit sourceInfo: SourceInfo) : Bool = this === UInt(0, 1)
+ def do_unary_! (implicit sourceInfo: SourceInfo) : Bool = this === 0.U(1)
override def do_<< (that: Int)(implicit sourceInfo: SourceInfo): UInt =
binop(sourceInfo, UInt(this.width + that), ShiftLeftOp, that)
@@ -501,7 +496,7 @@ sealed class UInt private[core] (width: Width, lit: Option[ULit] = None)
final def bitSet(off: UInt, dat: Bool): UInt = macro UIntTransform.bitset
def do_bitSet(off: UInt, dat: Bool)(implicit sourceInfo: SourceInfo): UInt = {
- val bit = UInt(1, 1) << off
+ val bit = 1.U(1) << off
Mux(dat, this | bit, ~(~this | bit))
}
@@ -532,89 +527,35 @@ sealed class UInt private[core] (width: Width, lit: Option[ULit] = None)
}
// This is currently a factory because both Bits and UInt inherit it.
-private[core] sealed trait UIntFactory {
+trait UIntFactory {
/** Create a UInt type with inferred width. */
def apply(): UInt = apply(Width())
/** Create a UInt port with specified width. */
def apply(width: Width): UInt = new UInt(width)
- /** Create a UInt with a specified width - compatibility with Chisel2. */
- def width(width: Int): UInt = apply(Width(width))
- /** Create a UInt port with specified width. */
- def width(width: Width): UInt = new UInt(width)
- /** Create a UInt literal with fixed width. */
- def apply(value: BigInt, width: Int): UInt = Lit(value, Width(width))
- /** Create a UInt literal with inferred width. */
- def apply(n: String): UInt = Lit(n)
- /** Create a UInt literal with fixed width. */
- def apply(n: String, width: Int): UInt = Lit(parse(n), width)
- /** Create a UInt literal with specified width. */
- def apply(value: BigInt, width: Width): UInt = Lit(value, width)
- def Lit(value: BigInt, width: Int): UInt = Lit(value, Width(width))
- /** Create a UInt literal with inferred width. */
- def Lit(value: BigInt): UInt = Lit(value, Width())
- def Lit(n: String): UInt = Lit(parse(n), parsedWidth(n))
- /** Create a UInt literal with fixed width. */
- def Lit(n: String, width: Int): UInt = Lit(parse(n), width)
+
/** Create a UInt literal with specified width. */
- def Lit(value: BigInt, width: Width): UInt = {
+ protected[chisel3] def Lit(value: BigInt, width: Width): UInt = {
val lit = ULit(value, width)
val result = new UInt(lit.width, Some(lit))
// Bind result to being an Literal
result.binding = LitBinding()
result
}
+
/** Create a UInt with the specified range */
def apply(range: Range): UInt = {
- width(range.getWidth)
+ apply(range.getWidth)
}
/** Create a UInt with the specified range */
def apply(range: (NumericBound[Int], NumericBound[Int])): UInt = {
apply(KnownUIntRange(range._1, range._2))
}
-
- /** Create a UInt with a specified width - compatibility with Chisel2. */
- // NOTE: This resolves UInt(width = 32)
- def apply(dir: Option[Direction] = None, width: Int): UInt = apply(Width(width))
- /** Create a UInt literal with inferred width.- compatibility with Chisel2. */
- def apply(value: BigInt): UInt = apply(value, Width())
- /** Create a UInt with a specified direction and width - compatibility with Chisel2. */
- def apply(dir: Direction, width: Int): UInt = apply(dir, Width(width))
- /** Create a UInt with a specified direction, but unspecified width - compatibility with Chisel2. */
- def apply(dir: Direction): UInt = apply(dir, Width())
- def apply(dir: Direction, wWidth: Width): UInt = {
- val result = apply(wWidth)
- dir match {
- case Direction.Input => Input(result)
- case Direction.Output => Output(result)
- case Direction.Unspecified => result
- }
- }
-
- private def parse(n: String) = {
- val (base, num) = n.splitAt(1)
- val radix = base match {
- case "x" | "h" => 16
- case "d" => 10
- case "o" => 8
- case "b" => 2
- case _ => Builder.error(s"Invalid base $base"); 2
- }
- BigInt(num.filterNot(_ == '_'), radix)
- }
-
- private def parsedWidth(n: String) =
- if (n(0) == 'b') {
- Width(n.length-1)
- } else if (n(0) == 'h') {
- Width((n.length-1) * 4)
- } else {
- Width()
- }
}
object UInt extends UIntFactory
+object Bits extends UIntFactory
-sealed class SInt private (width: Width, lit: Option[SLit] = None)
+sealed class SInt private[core] (width: Width, lit: Option[SLit] = None)
extends Bits(width, lit) with Num[SInt] {
private[core] override def cloneTypeWidth(w: Width): this.type =
@@ -622,13 +563,13 @@ sealed class SInt private (width: Width, lit: Option[SLit] = None)
private[chisel3] def toType = s"SInt$width"
override private[chisel3] def fromInt(value: BigInt, width: Int): this.type =
- SInt(value, width).asInstanceOf[this.type]
+ value.asSInt(width.W).asInstanceOf[this.type]
final def unary_- (): SInt = macro SourceInfoTransform.noArg
final def unary_-% (): SInt = macro SourceInfoTransform.noArg
- def unary_- (implicit sourceInfo: SourceInfo): SInt = SInt(0) - this
- def unary_-% (implicit sourceInfo: SourceInfo): SInt = SInt(0) -% this
+ def unary_- (implicit sourceInfo: SourceInfo): SInt = 0.S - this
+ def unary_-% (implicit sourceInfo: SourceInfo): SInt = 0.S -% this
/** add (default - no growth) operator */
override def do_+ (that: SInt)(implicit sourceInfo: SourceInfo): SInt =
@@ -696,7 +637,7 @@ sealed class SInt private (width: Width, lit: Option[SLit] = None)
final def abs(): UInt = macro SourceInfoTransform.noArg
- def do_abs(implicit sourceInfo: SourceInfo): UInt = Mux(this < SInt(0), (-this).asUInt, this.asUInt)
+ def do_abs(implicit sourceInfo: SourceInfo): UInt = Mux(this < 0.S, (-this).asUInt, this.asUInt)
override def do_<< (that: Int)(implicit sourceInfo: SourceInfo): SInt =
binop(sourceInfo, SInt(this.width + that), ShiftLeftOp, that)
@@ -718,65 +659,38 @@ sealed class SInt private (width: Width, lit: Option[SLit] = None)
}
}
-object SInt {
+trait SIntFactory {
/** Create an SInt type with inferred width. */
def apply(): SInt = apply(Width())
/** Create a SInt type or port with fixed width. */
def apply(width: Width): SInt = new SInt(width)
- /** Create a SInt type or port with fixed width. */
- def width(width: Int): SInt = apply(Width(width))
- /** Create an SInt type with specified width. */
- def width(width: Width): SInt = new SInt(width)
-
- /** Create an SInt literal with inferred width. */
- def apply(value: BigInt): SInt = Lit(value)
- /** Create an SInt literal with fixed width. */
- def apply(value: BigInt, width: Int): SInt = Lit(value, width)
-
- /** Create an SInt literal with specified width. */
- def apply(value: BigInt, width: Width): SInt = Lit(value, width)
/** Create a SInt with the specified range */
def apply(range: Range): SInt = {
- width(range.getWidth)
+ apply(range.getWidth)
}
/** Create a SInt with the specified range */
def apply(range: (NumericBound[Int], NumericBound[Int])): SInt = {
apply(KnownSIntRange(range._1, range._2))
}
- def Lit(value: BigInt): SInt = Lit(value, Width())
- def Lit(value: BigInt, width: Int): SInt = Lit(value, Width(width))
/** Create an SInt literal with specified width. */
- def Lit(value: BigInt, width: Width): SInt = {
-
+ protected[chisel3] def Lit(value: BigInt, width: Width): SInt = {
val lit = SLit(value, width)
val result = new SInt(lit.width, Some(lit))
// Bind result to being an Literal
result.binding = LitBinding()
result
}
- /** Create a SInt with a specified width - compatibility with Chisel2. */
- def apply(dir: Option[Direction] = None, width: Int): SInt = apply(Width(width))
- /** Create a SInt with a specified direction and width - compatibility with Chisel2. */
- def apply(dir: Direction, width: Int): SInt = apply(dir, Width(width))
- /** Create a SInt with a specified direction, but unspecified width - compatibility with Chisel2. */
- def apply(dir: Direction): SInt = apply(dir, Width())
- def apply(dir: Direction, wWidth: Width): SInt = {
- val result = apply(wWidth)
- dir match {
- case Direction.Input => Input(result)
- case Direction.Output => Output(result)
- case Direction.Unspecified => result
- }
- }
}
+object SInt extends SIntFactory
+
// REVIEW TODO: Why does this extend UInt and not Bits? Does defining airth
// operations on a Bool make sense?
/** A data type for booleans, defined as a single bit indicating true or false.
*/
-sealed class Bool(lit: Option[ULit] = None) extends UInt(Width(1), lit) {
+sealed class Bool(lit: Option[ULit] = None) extends UInt(1.W, lit) {
private[core] override def cloneTypeWidth(w: Width): this.type = {
require(!w.known || w.get == 1)
new Bool().asInstanceOf[this.type]
@@ -784,7 +698,7 @@ sealed class Bool(lit: Option[ULit] = None) extends UInt(Width(1), lit) {
override private[chisel3] def fromInt(value: BigInt, width: Int): this.type = {
require((value == 0 || value == 1) && width == 1)
- Bool(value == 1).asInstanceOf[this.type]
+ (value == 1).asBool.asInstanceOf[this.type]
}
// REVIEW TODO: Why does this need to exist and have different conventions
@@ -822,31 +736,23 @@ sealed class Bool(lit: Option[ULit] = None) extends UInt(Width(1), lit) {
def do_asClock(implicit sourceInfo: SourceInfo): Clock = pushOp(DefPrim(sourceInfo, Clock(), AsClockOp, ref))
}
-object Bool {
+trait BoolFactory {
/** Creates an empty Bool.
*/
def apply(): Bool = new Bool()
/** Creates Bool literal.
*/
- def apply(x: Boolean): Bool = Lit(x)
- def Lit(x: Boolean): Bool = {
+ protected[chisel3] def Lit(x: Boolean): Bool = {
val result = new Bool(Some(ULit(if (x) 1 else 0, Width(1))))
// Bind result to being an Literal
result.binding = LitBinding()
result
}
- /** Create a UInt with a specified direction and width - compatibility with Chisel2. */
- def apply(dir: Direction): Bool = {
- val result = apply()
- dir match {
- case Direction.Input => Input(result)
- case Direction.Output => Output(result)
- case Direction.Unspecified => result
- }
- }
}
+object Bool extends BoolFactory
+
object Mux {
/** Creates a mux, whose output is one of the inputs depending on the
* value of the condition.
@@ -856,7 +762,7 @@ object Mux {
* @param alt the value chosen when `cond` is false
* @example
* {{{
- * val muxOut = Mux(data_in === UInt(3), UInt(3, 4), UInt(0, 4))
+ * val muxOut = Mux(data_in === 3.U, 3.U(4.W), 0.U(4.W))
* }}}
*/
def apply[T <: Data](cond: Bool, con: T, alt: T): T = macro MuxTransform.apply[T]
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Mem.scala b/chiselFrontend/src/main/scala/chisel3/core/Mem.scala
index a43b19fe..1863e921 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Mem.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Mem.scala
@@ -40,7 +40,7 @@ sealed abstract class MemBase[T <: Data](t: T, val length: Int) extends HasId wi
*/
def apply(idx: Int): T = {
require(idx >= 0 && idx < length)
- apply(UInt(idx))
+ apply(idx.asUInt)
}
/** Creates a read/write accessor into the memory with dynamic addressing.
diff --git a/chiselFrontend/src/main/scala/chisel3/core/SeqUtils.scala b/chiselFrontend/src/main/scala/chisel3/core/SeqUtils.scala
index 558dea7a..e435860e 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/SeqUtils.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/SeqUtils.scala
@@ -25,12 +25,12 @@ private[chisel3] object SeqUtils {
}
}
- /** Outputs the number of elements that === Bool(true).
+ /** Outputs the number of elements that === true.B.
*/
def count(in: Seq[Bool]): UInt = macro SourceInfoTransform.inArg
def do_count(in: Seq[Bool])(implicit sourceInfo: SourceInfo): UInt = in.size match {
- case 0 => UInt(0)
+ case 0 => 0.U
case 1 => in.head
case n => count(in take n/2) +& count(in drop n/2)
}
@@ -57,7 +57,7 @@ private[chisel3] object SeqUtils {
if (in.tail.isEmpty) {
in.head._2
} else {
- val masked = for ((s, i) <- in) yield Mux(s, i.asUInt, UInt(0))
+ val masked = for ((s, i) <- in) yield Mux(s, i.asUInt, 0.U)
val width = in.map(_._2.width).reduce(_ max _)
in.head._2.cloneTypeWidth(width).fromBits(masked.reduceLeft(_|_))
}
diff --git a/chiselFrontend/src/main/scala/chisel3/core/When.scala b/chiselFrontend/src/main/scala/chisel3/core/When.scala
index 196e7903..7501ebb1 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/When.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/When.scala
@@ -18,9 +18,9 @@ object when { // scalastyle:ignore object.name
*
* @example
* {{{
- * when ( myData === UInt(3) ) {
+ * when ( myData === 3.U ) {
* // Some logic to run when myData equals 3.
- * } .elsewhen ( myData === UInt(1) ) {
+ * } .elsewhen ( myData === 1.U ) {
* // Some logic to run when myData equals 1.
* } .otherwise {
* // Some logic to run when myData is neither 3 nor 1.
diff --git a/chiselFrontend/src/main/scala/chisel3/core/package.scala b/chiselFrontend/src/main/scala/chisel3/core/package.scala
new file mode 100644
index 00000000..77f35c23
--- /dev/null
+++ b/chiselFrontend/src/main/scala/chisel3/core/package.scala
@@ -0,0 +1,106 @@
+package chisel3 {
+ import internal.Builder
+
+ package object core {
+ import internal.firrtl.Width
+
+ /**
+ * These implicit classes allow one to convert scala.Int|scala.BigInt to
+ * Chisel.UInt|Chisel.SInt by calling .asUInt|.asSInt on them, respectively.
+ * The versions .asUInt(width)|.asSInt(width) are also available to explicitly
+ * mark a width for the new literal.
+ *
+ * Also provides .asBool to scala.Boolean and .asUInt to String
+ *
+ * Note that, for stylistic reasons, one should avoid extracting immediately
+ * after this call using apply, ie. 0.asUInt(1)(0) due to potential for
+ * confusion (the 1 is a bit length and the 0 is a bit extraction position).
+ * Prefer storing the result and then extracting from it.
+ */
+ implicit class fromBigIntToLiteral(val bigint: BigInt) {
+ /** Int to UInt conversion, recommended style for constants.
+ */
+ def U: UInt = UInt.Lit(bigint, Width()) // scalastyle:ignore method.name
+ /** Int to SInt conversion, recommended style for constants.
+ */
+ def S: SInt = SInt.Lit(bigint, Width()) // scalastyle:ignore method.name
+ /** Int to UInt conversion with specified width, recommended style for constants.
+ */
+ def U(width: Width): UInt = UInt.Lit(bigint, width) // scalastyle:ignore method.name
+ /** Int to SInt conversion with specified width, recommended style for constants.
+ */
+ def S(width: Width): SInt = SInt.Lit(bigint, width) // scalastyle:ignore method.name
+
+ /** Int to UInt conversion, recommended style for variables.
+ */
+ def asUInt: UInt = UInt.Lit(bigint, Width())
+ /** Int to SInt conversion, recommended style for variables.
+ */
+ def asSInt: SInt = SInt.Lit(bigint, Width())
+ /** Int to UInt conversion with specified width, recommended style for variables.
+ */
+ def asUInt(width: Width): UInt = UInt.Lit(bigint, width)
+ /** Int to SInt conversion with specified width, recommended style for variables.
+ */
+ def asSInt(width: Width): SInt = SInt.Lit(bigint, width)
+ }
+
+ implicit class fromIntToLiteral(val int: Int) extends fromBigIntToLiteral(int)
+ implicit class fromLongToLiteral(val long: Long) extends fromBigIntToLiteral(long)
+
+ implicit class fromStringToLiteral(val str: String) {
+ /** String to UInt parse, recommended style for constants.
+ */
+ def U: UInt = UInt.Lit(parse(str), parsedWidth(str)) // scalastyle:ignore method.name
+ /** String to UInt parse with specified width, recommended style for constants.
+ */
+ def U(width: Width): UInt = UInt.Lit(parse(str), width) // scalastyle:ignore method.name
+
+ /** String to UInt parse, recommended style for variables.
+ */
+ def asUInt: UInt = UInt.Lit(parse(str), parsedWidth(str))
+ /** String to UInt parse with specified width, recommended style for variables.
+ */
+ def asUInt(width: Width): UInt = UInt.Lit(parse(str), width)
+
+ protected def parse(n: String) = {
+ val (base, num) = n.splitAt(1)
+ val radix = base match {
+ case "x" | "h" => 16
+ case "d" => 10
+ case "o" => 8
+ case "b" => 2
+ case _ => Builder.error(s"Invalid base $base"); 2
+ }
+ BigInt(num.filterNot(_ == '_'), radix)
+ }
+
+ protected def parsedWidth(n: String) =
+ if (n(0) == 'b') {
+ Width(n.length-1)
+ } else if (n(0) == 'h') {
+ Width((n.length-1) * 4)
+ } else {
+ Width()
+ }
+ }
+
+ implicit class fromBooleanToLiteral(val boolean: Boolean) {
+ /** Boolean to Bool conversion, recommended style for constants.
+ */
+ def B: Bool = Bool.Lit(boolean) // scalastyle:ignore method.name
+
+ /** Boolean to Bool conversion, recommended style for variables.
+ */
+ def asBool: Bool = Bool.Lit(boolean)
+ }
+
+ implicit class fromDoubleToLiteral(val double: Double) {
+ def F(binaryPoint: Int): FixedPoint = FixedPoint.fromDouble(double, binaryPoint = binaryPoint)
+ }
+
+ implicit class fromIntToWidth(val int: Int) {
+ def W: Width = Width(int) // scalastyle:ignore method.name
+ }
+ }
+}