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authorJim Lawson2016-08-10 17:07:31 -0700
committerDonggyu Kim2016-08-16 11:27:47 -0700
commit0744b3e5f9c0648878b97d3375cd7d88e2d0ee08 (patch)
tree77fc8b2c28263dc055d78452dc31a70517c5efa2 /chiselFrontend/src/main/scala/chisel3/core
parente1e7c7ea3359df1351ba979287b62458e411e846 (diff)
Add component to signature.
Diffstat (limited to 'chiselFrontend/src/main/scala/chisel3/core')
-rw-r--r--chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala3
1 files changed, 1 insertions, 2 deletions
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala b/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala
index 15643ac8..de64cb3d 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala
@@ -374,5 +374,4 @@ class Bundle extends Aggregate(NO_DIR) {
private[core] object Bundle {
val keywords = List("flip", "asInput", "asOutput", "cloneType", "toBits",
- "widthOption")
-}
+ "widthOption", "signalName", "signalPathName", "signalParent", "signalComponent")