diff options
| author | Jack Koenig | 2017-04-04 13:35:03 -0700 |
|---|---|---|
| committer | GitHub | 2017-04-04 13:35:03 -0700 |
| commit | 00796dfce1ec3eba739467571cdfc52df2aa62de (patch) | |
| tree | deac465ccf59e9687d1d307b7d9fa1fde4ee0b47 /chiselFrontend/src/main/scala/chisel3/core | |
| parent | 0a36785778fb031dd01d82af3763bee997bf895f (diff) | |
Use input element to decide if Vec of values has direction (#570)
Using the sample_element of the created wire is incorrect because Wires have no
direction so the Wire constructed for a Vec of Module IO was constructed
incorrectly. Fixes #569 and resolves #522.
Diffstat (limited to 'chiselFrontend/src/main/scala/chisel3/core')
| -rw-r--r-- | chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala b/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala index a561e7d5..be874042 100644 --- a/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala @@ -73,7 +73,9 @@ object Vec { def doConnect(sink: T, source: T) = { // TODO: this looks bad, and should feel bad. Replace with a better abstraction. - val hasDirectioned = vec.sample_element match { + // NOTE: Must use elts.head instead of vec.sample_element because vec.sample_element has + // WireBinding which does not have a direction + val hasDirectioned = elts.head match { case t: Aggregate => t.flatten.exists(_.dir != Direction.Unspecified) case t: Element => t.dir != Direction.Unspecified } |
