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authorChick Markley2017-02-15 09:45:16 -0800
committerGitHub2017-02-15 09:45:16 -0800
commit41bee3f347e743e328ee520a48109cb542f3b245 (patch)
tree3dba38b3f8f04d87466f7bb258ae338347235fbe /chiselFrontend/src/main/scala/chisel3/core/package.scala
parentabb05d0569dd6b6c3e736a4db2ea739d767b3c3f (diff)
Fixed point factory stuff (#505)
* Don't allow analog to analog monoconnect adjust tests accordingly * demonstrate bit loss in shift right for fixed point * cleaned up some stuff. this does not test clean due to bug in firrtl
Diffstat (limited to 'chiselFrontend/src/main/scala/chisel3/core/package.scala')
-rw-r--r--chiselFrontend/src/main/scala/chisel3/core/package.scala10
1 files changed, 10 insertions, 0 deletions
diff --git a/chiselFrontend/src/main/scala/chisel3/core/package.scala b/chiselFrontend/src/main/scala/chisel3/core/package.scala
index 9fa20f49..aec5398d 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/package.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/package.scala
@@ -1,3 +1,5 @@
+// See LICENSE for license details.
+
package chisel3 {
import internal.Builder
@@ -93,8 +95,16 @@ package chisel3 {
def asBool(): Bool = Bool.Lit(boolean)
}
+ //scalastyle:off method.name
implicit class fromDoubleToLiteral(val double: Double) {
+ @deprecated("Use notation <double>.F(<binary_point>.BP) instead", "chisel3")
def F(binaryPoint: Int): FixedPoint = FixedPoint.fromDouble(double, binaryPoint = binaryPoint)
+ def F(binaryPoint: BinaryPoint): FixedPoint = {
+ FixedPoint.fromDouble(double, Width(), binaryPoint)
+ }
+ def F(width: Width, binaryPoint: BinaryPoint): FixedPoint = {
+ FixedPoint.fromDouble(double, width, binaryPoint)
+ }
}
implicit class fromIntToWidth(val int: Int) {