diff options
| author | Richard Lin | 2017-08-11 13:05:44 -0700 |
|---|---|---|
| committer | GitHub | 2017-08-11 13:05:44 -0700 |
| commit | c87145bc61a729bb035428d527c5787c174c5256 (patch) | |
| tree | 99f9dbe4f3fca852a4e890619d5dace0cb3677dd /chiselFrontend/src/main/scala/chisel3/core/UserModule.scala | |
| parent | 43e62e7f6b5534b48c3757cfcca51b66ca74753d (diff) | |
Rename userDir->specifiedDir (#671)
Diffstat (limited to 'chiselFrontend/src/main/scala/chisel3/core/UserModule.scala')
| -rw-r--r-- | chiselFrontend/src/main/scala/chisel3/core/UserModule.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/chiselFrontend/src/main/scala/chisel3/core/UserModule.scala b/chiselFrontend/src/main/scala/chisel3/core/UserModule.scala index 5207ef04..8b176c3b 100644 --- a/chiselFrontend/src/main/scala/chisel3/core/UserModule.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/UserModule.scala @@ -64,7 +64,7 @@ abstract class UserModule(implicit moduleCompileOptions: CompileOptions) id._onModuleClose } - val firrtlPorts = getModulePorts map {port => Port(port, port.userDirection)} + val firrtlPorts = getModulePorts map {port => Port(port, port.specifiedDirection)} _firrtlPorts = Some(firrtlPorts) // Generate IO invalidation commands to initialize outputs as unused |