Invalidateapi (#645)

* Require explicit connection to DontCare to generate "is invalid".

* Add tests for RefNotInitializedException.
Currently, we fail the when ... otherwise ...

* Disable ScalaTest shrinking on error in ComplexAssignSpec.

* fix broken merge; still some binding issues

* cleanup DontCare connection checks; add missing directions to test module IOs

* Have library code inherit compileOptions from the enclosing Module (if it exists).

* work around current firrtl uninitialized references with Strict compile options and explicitInvalidate

* more CompileOptions cleanup; move test-specific defines to package object

* minimize differences with master

* set default CompileOptions.explicitInvalidate to false until we fix the FIRRTL when issue

* ignore the StrictCompiler property checks (until  CompileOptions.explicitInvalidate is defaulted to true)

* Revert "more CompileOptions cleanup; move test-specific defines to package object"

This reverts commit e4486edcba990d150e76e08a2fc6abca033556e0.

* Revert "work around current firrtl uninitialized references with Strict compile options and explicitInvalidate"

This reverts commit 426faa430a62c3dac2dbdf33044d3386d4243157.

* remove unused code

* Convert to binding-based DontCare implementation

* comment cleanup to minimize differences with master

* Tentatively remove possibly redundant DefInvalid on module ports.

* Respond to code review change request.
- backout build.sbt change
- correct indentation
- handle bulk of DontCare semantics in elemConnect()
- have DontCare extend Element, not Data (eliminate most Object specific methods
- add comments indicating reason for explicit DontCare connections

* Initialize test elements without requiring a DontCare.

* Respond to review change requests.
- DontCare should work on left or right side in BiDirectional connections
- call bind() to set DontCare binding instead of messing with internal variables
- DontCares are only equivalent with DontCares
- clean up processWhens() definition

* Eliminate DontCare connection to inputs in MonoConnect().

* Pull aggregates apart for the purpose of DontCare connections.

* Restore the explicit (conditionally executed) ports DefInvalidin ImplicitModule()

* Don't add DontCare's to the module list of _ids.

* Add missing DefInvalid() to LegacyModule().

* Respond to review requests: add DontCare BiConnect Vec, remove null parent hack to avoid addId(), initialize singletons early in Builder

* Move DontCare out of chisel3.experimental.

1 files changed, 16 insertions, 7 deletions

diff --git a/chiselFrontend/src/main/scala/chisel3/core/UserModule.scala b/chiselFrontend/src/main/scala/chisel3/core/UserModule.scala
index 218b27c6..c99d53cf 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/UserModule.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/UserModule.scala
@@ -67,9 +67,15 @@ abstract class UserModule(implicit moduleCompileOptions: CompileOptions)
     val firrtlPorts = getModulePorts map {port => Port(port, port.specifiedDirection)}
     _firrtlPorts = Some(firrtlPorts)
 
-    // Generate IO invalidation commands to initialize outputs as unused
-    val invalidateCommands = getModulePorts map {port => DefInvalid(UnlocatableSourceInfo, port.ref)}
-
+    // Generate IO invalidation commands to initialize outputs as unused,
+    //  unless the client wants explicit control over their generation.
+    val invalidateCommands = {
+      if (!compileOptions.explicitInvalidate) {
+        getModulePorts map { port => DefInvalid(UnlocatableSourceInfo, port.ref) }
+      } else {
+        Seq()
+      }
+    }
     val component = DefModule(this, name, firrtlPorts, invalidateCommands ++ getCommands)
     _component = Some(component)
     component
@@ -97,10 +103,11 @@ abstract class ImplicitModule(implicit moduleCompileOptions: CompileOptions)
   private[core] override def initializeInParent() {
     implicit val sourceInfo = UnlocatableSourceInfo
 
-    for (port <- getModulePorts) {
-      pushCommand(DefInvalid(sourceInfo, port.ref))
+    if (!compileOptions.explicitInvalidate) {
+      for (port <- getModulePorts) {
+        pushCommand(DefInvalid(sourceInfo, port.ref))
+      }
     }
-
     clock := Builder.forcedClock
     reset := Builder.forcedReset
   }
@@ -171,7 +178,9 @@ abstract class LegacyModule(implicit moduleCompileOptions: CompileOptions)
     // module de-duplication in FIRRTL emission.
     implicit val sourceInfo = UnlocatableSourceInfo
 
-    pushCommand(DefInvalid(sourceInfo, io.ref))
+    if (!compileOptions.explicitInvalidate) {
+      pushCommand(DefInvalid(sourceInfo, io.ref))
+    }
 
     override_clock match {
       case Some(override_clock) => clock := override_clock