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authorducky2017-11-03 18:34:46 -0700
committerRichard Lin2018-01-02 13:41:13 -0800
commit7c3c18de2ffd56af51b99030c7ae7d3a321aed5f (patch)
tree55bc9cbb4cf5a1ba6c2d3e4c57dd9e3b6367060c /chiselFrontend/src/main/scala/chisel3/core/UserModule.scala
parentcb7fcd2b18135230dc40f3c7bb98685e7ffde9d5 (diff)
Autoclonetype initial prototype
Diffstat (limited to 'chiselFrontend/src/main/scala/chisel3/core/UserModule.scala')
-rw-r--r--chiselFrontend/src/main/scala/chisel3/core/UserModule.scala6
1 files changed, 3 insertions, 3 deletions
diff --git a/chiselFrontend/src/main/scala/chisel3/core/UserModule.scala b/chiselFrontend/src/main/scala/chisel3/core/UserModule.scala
index 9c923037..ac87eda5 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/UserModule.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/UserModule.scala
@@ -151,8 +151,8 @@ abstract class LegacyModule(implicit moduleCompileOptions: CompileOptions)
def io: Record
// Allow access to bindings from the compatibility package
- protected def _ioPortBound() = portsContains(io)
-
+ protected def _compatIoPortBound() = portsContains(io)
+
protected override def nameIds(rootClass: Class[_]): HashMap[HasId, String] = {
val names = super.nameIds(rootClass)
@@ -165,7 +165,7 @@ abstract class LegacyModule(implicit moduleCompileOptions: CompileOptions)
}
private[core] override def generateComponent(): Component = {
- _autoWrapPorts() // pre-IO(...) compatibility hack
+ _compatAutoWrapPorts() // pre-IO(...) compatibility hack
// Restrict IO to just io, clock, and reset
require(io != null, "Module must have io")