Fix treatment of Vec of Analog and Vec of Bundle of Analog (#1091)

* IO(Analog) fixed for RawModule

* Add a Analog Port for RawModule test & spec

* Fixes around Module instantiation and ports in AnalogPortRawModuleTest

* Shorten Comment

* Add Data.isSynthesizable to distinguish SampleElementBinding

This helps clarify the notion of being bound but not hardware.
Data.topBindingOpt is now used to get the *actual* top binding,
including across SampleElements (eg. in Analog checking that the top is
bound to a Port or a Wire)

* Fix pretty printing for Vec

* Refactor tests for Vec of Analog, add test for Vec of Bundle of Analog

1 files changed, 1 insertions, 1 deletions

diff --git a/chiselFrontend/src/main/scala/chisel3/core/StrongEnum.scala b/chiselFrontend/src/main/scala/chisel3/core/StrongEnum.scala
index 1689e6ad..63f7a8a0 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/StrongEnum.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/StrongEnum.scala
@@ -161,7 +161,7 @@ abstract class EnumType(private val factory: EnumFactory, selfAnnotating: Boolea
     super.bind(target, parentDirection)
 
     // Make sure we only annotate hardware and not literals
-    if (selfAnnotating && topBindingOpt.isDefined && topBindingOpt.get.isInstanceOf[ConstrainedBinding]) {
+    if (selfAnnotating && isSynthesizable && topBindingOpt.get.isInstanceOf[ConstrainedBinding]) {
       annotateEnum()
     }
   }