diff options
| author | Richard Lin | 2017-04-26 17:52:29 -0700 |
|---|---|---|
| committer | GitHub | 2017-04-26 17:52:29 -0700 |
| commit | 36718cf6040990f2be9ab143adb1d3c519e9d983 (patch) | |
| tree | 34ae121faf999bb962f5257c26de651bd08ecf04 /chiselFrontend/src/main/scala/chisel3/core/SeqUtils.scala | |
| parent | 7449fdc9043708e426aeb8b12b30226db9e47a80 (diff) | |
Deprecate fromBits and clock/reset constructors (#583)
Diffstat (limited to 'chiselFrontend/src/main/scala/chisel3/core/SeqUtils.scala')
| -rw-r--r-- | chiselFrontend/src/main/scala/chisel3/core/SeqUtils.scala | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/chiselFrontend/src/main/scala/chisel3/core/SeqUtils.scala b/chiselFrontend/src/main/scala/chisel3/core/SeqUtils.scala index 49e96ddf..69f54102 100644 --- a/chiselFrontend/src/main/scala/chisel3/core/SeqUtils.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/SeqUtils.scala @@ -70,7 +70,7 @@ private[chisel3] object SeqUtils { def buildAndOrMultiplexor[TT <: Data](inputs: Iterable[(Bool, TT)]): T = { val masked = for ((s, i) <- inputs) yield Mux(s, i.asUInt(), 0.U) - output.fromBits(masked.reduceLeft(_ | _)) + masked.reduceLeft(_ | _).asTypeOf(output) } output match { @@ -82,7 +82,7 @@ private[chisel3] object SeqUtils { } val masked = for ((s, i) <- sInts) yield Mux(s, i, 0.S) - output.fromBits(masked.reduceLeft(_ | _)) + masked.reduceLeft(_ | _).asTypeOf(output) case _: FixedPoint => val (sels, possibleOuts) = in.toSeq.unzip |
