diff options
| author | Richard Lin | 2017-04-13 22:59:00 -0700 |
|---|---|---|
| committer | GitHub | 2017-04-13 22:59:00 -0700 |
| commit | e07248b8f6022fafdb84f5d1c0ebe3fc90a5475a (patch) | |
| tree | f2bb938fd35651b4fc7b88cbcd20e163cc75dd2e /chiselFrontend/src/main/scala/chisel3/core/Reg.scala | |
| parent | 97902cdc53eec52aa0cd806b8cb49a0e3f2fb769 (diff) | |
Module Hierarchy Refactor (#469)
Diffstat (limited to 'chiselFrontend/src/main/scala/chisel3/core/Reg.scala')
| -rw-r--r-- | chiselFrontend/src/main/scala/chisel3/core/Reg.scala | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Reg.scala b/chiselFrontend/src/main/scala/chisel3/core/Reg.scala index 715bdd70..12d0a939 100644 --- a/chiselFrontend/src/main/scala/chisel3/core/Reg.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/Reg.scala @@ -22,7 +22,7 @@ object Reg { val reg = t.chiselCloneType val clock = Node(Builder.forcedClock) - Binding.bind(reg, RegBinder(Builder.forcedModule), "Error: t") + Binding.bind(reg, RegBinder(Builder.forcedUserModule), "Error: t") pushCommand(DefReg(sourceInfo, reg, clock)) reg } @@ -90,7 +90,7 @@ object RegInit { val clock = Node(Builder.forcedClock) val reset = Node(Builder.forcedReset) - Binding.bind(reg, RegBinder(Builder.forcedModule), "Error: t") + Binding.bind(reg, RegBinder(Builder.forcedUserModule), "Error: t") Binding.checkSynthesizable(init, s"'init' ($init)") pushCommand(DefRegInit(sourceInfo, reg, clock, reset, init.ref)) reg |