Merge pull request #265 from ucb-bar/gsdt

Gsdt - Fixup to Chisel connections and direction - PR 200 revisited.

1 files changed, 17 insertions, 8 deletions

diff --git a/chiselFrontend/src/main/scala/chisel3/core/Reg.scala b/chiselFrontend/src/main/scala/chisel3/core/Reg.scala
index b0dd3bb1..9d380695 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Reg.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Reg.scala
@@ -8,15 +8,18 @@ import chisel3.internal.firrtl._
 import chisel3.internal.sourceinfo.{SourceInfo, UnlocatableSourceInfo}
 
 object Reg {
-  private[core] def makeType[T <: Data](t: T = null, next: T = null, init: T = null): T = {
+  private[core] def makeType[T <: Data](compileOptions: CompileOptions, t: T = null, next: T = null, init: T = null): T = {
     if (t ne null) {
-      t.cloneType
+      if (compileOptions.declaredTypeMustBeUnbound) {
+        Binding.checkUnbound(t, s"t ($t) must be unbound Type. Try using cloneType?")
+      }
+      t.chiselCloneType
     } else if (next ne null) {
       next.cloneTypeWidth(Width())
     } else if (init ne null) {
       init.litArg match {
         // For e.g. Reg(init=UInt(0, k)), fix the Reg's width to k
-        case Some(lit) if lit.forcedWidth => init.cloneType
+        case Some(lit) if lit.forcedWidth => init.chiselCloneType
         case _ => init.cloneTypeWidth(Width())
       }
     } else {
@@ -37,18 +40,18 @@ object Reg {
     * is a valid value. In those cases, you can either use the outType only Reg
     * constructor or pass in `null.asInstanceOf[T]`.
     */
-  def apply[T <: Data](t: T = null, next: T = null, init: T = null): T =
+  def apply[T <: Data](t: T = null, next: T = null, init: T = null)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): T =
     // Scala macros can't (yet) handle named or default arguments.
-    do_apply(t, next, init)(UnlocatableSourceInfo)
+    do_apply(t, next, init)(sourceInfo, compileOptions)
 
   /** Creates a register without initialization (reset is ignored). Value does
     * not change unless assigned to (using the := operator).
     *
     * @param outType: data type for the register
     */
-  def apply[T <: Data](outType: T): T = Reg[T](outType, null.asInstanceOf[T], null.asInstanceOf[T])
+  def apply[T <: Data](outType: T)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): T = Reg[T](outType, null.asInstanceOf[T], null.asInstanceOf[T])(sourceInfo, compileOptions)
 
-  def do_apply[T <: Data](t: T, next: T, init: T)(implicit sourceInfo: SourceInfo): T = {
+  def do_apply[T <: Data](t: T, next: T, init: T)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions = chisel3.core.ExplicitCompileOptions.NotStrict): T = {
     // TODO: write this in a way that doesn't need nulls (bad Scala style),
     // null.asInstanceOf[T], and two constructors. Using Option types are an
     // option, but introduces cumbersome syntax (wrap everything in a Some()).
@@ -56,14 +59,20 @@ object Reg {
     // but Scala's type inferencer and implicit insertion isn't smart enough
     // to resolve all use cases. If the type inferencer / implicit resolution
     // system improves, this may be changed.
-    val x = makeType(t, next, init)
+    val x = makeType(compileOptions, t, next, init)
     val clock = Node(x._parent.get.clock) // TODO multi-clock
+
+    // Bind each element of x to being a Reg
+    Binding.bind(x, RegBinder(Builder.forcedModule), "Error: t")
+
     if (init == null) {
       pushCommand(DefReg(sourceInfo, x, clock))
     } else {
+      Binding.checkSynthesizable(init, s"'init' ($init)")
       pushCommand(DefRegInit(sourceInfo, x, clock, Node(x._parent.get.reset), init.ref))
     }
     if (next != null) {
+      Binding.checkSynthesizable(next, s"'next' ($next)")
       x := next
     }
     x