diff options
| author | Richard Lin | 2017-08-17 17:24:02 -0700 |
|---|---|---|
| committer | Jack Koenig | 2017-08-17 17:24:02 -0700 |
| commit | 6e12ed9fd7a771eb30f44b8e1c4ab33f6ad8e0a6 (patch) | |
| tree | 0ff452193d515adc32ecccacb2b58daa9a1d95cb /chiselFrontend/src/main/scala/chisel3/core/Reg.scala | |
| parent | 802cfc4405c28ae212a955a92c7a6ad2d2b6f0c2 (diff) | |
More of the bindings refactor (#635)
Rest of the binding refactor
Diffstat (limited to 'chiselFrontend/src/main/scala/chisel3/core/Reg.scala')
| -rw-r--r-- | chiselFrontend/src/main/scala/chisel3/core/Reg.scala | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Reg.scala b/chiselFrontend/src/main/scala/chisel3/core/Reg.scala index 3fdb3398..19bbee1c 100644 --- a/chiselFrontend/src/main/scala/chisel3/core/Reg.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/Reg.scala @@ -40,6 +40,7 @@ object RegNext { }).asInstanceOf[T] val reg = Reg(model) + requireIsHardware(next, "reg next") reg := next reg @@ -56,6 +57,7 @@ object RegNext { }).asInstanceOf[T] val reg = RegInit(model, init) // TODO: this makes NO sense + requireIsHardware(next, "reg next") reg := next reg |