diff options
| author | ducky | 2018-06-28 14:53:00 -0700 |
|---|---|---|
| committer | Richard Lin | 2018-07-04 18:39:28 -0500 |
| commit | 4cf5caf86a072bc4af581536930469b82796dd27 (patch) | |
| tree | 5f3e4f1b8dd2cfc268dfbc84b5edb856c6d02c3a /chiselFrontend/src/main/scala/chisel3/core/Reg.scala | |
| parent | 28261aefc081a9edfff1cd67d2a4a386933dcb4b (diff) | |
properly fix undefined clock/reset issues
Diffstat (limited to 'chiselFrontend/src/main/scala/chisel3/core/Reg.scala')
| -rw-r--r-- | chiselFrontend/src/main/scala/chisel3/core/Reg.scala | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Reg.scala b/chiselFrontend/src/main/scala/chisel3/core/Reg.scala index 16244d12..11611c82 100644 --- a/chiselFrontend/src/main/scala/chisel3/core/Reg.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/Reg.scala @@ -84,8 +84,8 @@ object RegInit { requireIsChiselType(t, "reg type") } val reg = t.cloneTypeFull - val clock = Node(Builder.forcedClock) - val reset = Node(Builder.forcedReset) + val clock = Builder.forcedClock.ref + val reset = Builder.forcedReset.ref reg.bind(RegBinding(Builder.forcedUserModule)) requireIsHardware(init, "reg initializer") |