diff options
| author | Jim Lawson | 2016-09-29 15:43:34 -0700 |
|---|---|---|
| committer | Jim Lawson | 2016-09-29 15:43:34 -0700 |
| commit | 398edafd809c3abda751432c51a07b6b1158ecbd (patch) | |
| tree | e6db343182319954ad98570a2310a3d0ef298d9a /chiselFrontend/src/main/scala/chisel3/core/Reg.scala | |
| parent | 96fb6a5e2c781b20470d02eac186b1b129c20bdf (diff) | |
Manual dead code elimination.
Diffstat (limited to 'chiselFrontend/src/main/scala/chisel3/core/Reg.scala')
| -rw-r--r-- | chiselFrontend/src/main/scala/chisel3/core/Reg.scala | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Reg.scala b/chiselFrontend/src/main/scala/chisel3/core/Reg.scala index 30c2b3cd..9d380695 100644 --- a/chiselFrontend/src/main/scala/chisel3/core/Reg.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/Reg.scala @@ -6,7 +6,6 @@ import chisel3.internal._ import chisel3.internal.Builder.pushCommand import chisel3.internal.firrtl._ import chisel3.internal.sourceinfo.{SourceInfo, UnlocatableSourceInfo} -//import chisel3.CompileOptions object Reg { private[core] def makeType[T <: Data](compileOptions: CompileOptions, t: T = null, next: T = null, init: T = null): T = { |