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| author | Schuyler Eldridge | 2019-05-09 20:13:54 -0400 |
|---|---|---|
| committer | GitHub | 2019-05-09 20:13:54 -0400 |
| commit | e02d25c2d9310291a3084821713bd8d9b2325651 (patch) | |
| tree | 82453617fec3957e33724eb3a0fd25dd060d803f /chiselFrontend/src/main/scala/chisel3/core/RawModule.scala | |
| parent | 6be76f79f873873497e40fa647f9456391b4d59a (diff) | |
| parent | 356d5c99c233540e4d993ccc365a7069d9d2beaa (diff) | |
Merge pull request #1092 from freechipsproject/lfsr-async-reset
LFSR/PRNG Asynchronous Safety, Use Vec[Bool] to store internal state
Diffstat (limited to 'chiselFrontend/src/main/scala/chisel3/core/RawModule.scala')
0 files changed, 0 insertions, 0 deletions