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authorJim Lawson2016-09-30 12:13:58 -0700
committerGitHub2016-09-30 12:13:58 -0700
commitdb25e8180a53fb8f4912fd37b7a613e15a01564f (patch)
tree8bb5597746002ac98641f394cee4c94e1d154aff /chiselFrontend/src/main/scala/chisel3/core/Printf.scala
parent785620b1403d827986bf60c2a001d8d6f71eed72 (diff)
parent6edbdf279257d656b5eac38d9de8645a068611bf (diff)
Merge pull request #265 from ucb-bar/gsdt
Gsdt - Fixup to Chisel connections and direction - PR 200 revisited.
Diffstat (limited to 'chiselFrontend/src/main/scala/chisel3/core/Printf.scala')
-rw-r--r--chiselFrontend/src/main/scala/chisel3/core/Printf.scala4
1 files changed, 2 insertions, 2 deletions
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Printf.scala b/chiselFrontend/src/main/scala/chisel3/core/Printf.scala
index 55197425..4ec13751 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Printf.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Printf.scala
@@ -56,13 +56,13 @@ object printf { // scalastyle:ignore object.name
* @param pable [[Printable]] to print
*/
def apply(pable: Printable)(implicit sourceInfo: SourceInfo): Unit = {
- when (!Builder.dynamicContext.currentModule.get.reset) {
+ when (!Builder.forcedModule.reset) {
printfWithoutReset(pable)
}
}
private[chisel3] def printfWithoutReset(pable: Printable)(implicit sourceInfo: SourceInfo): Unit = {
- val clock = Builder.dynamicContext.currentModule.get.clock
+ val clock = Builder.forcedModule.clock
pushCommand(Printf(sourceInfo, Node(clock), pable))
}
private[chisel3] def printfWithoutReset(fmt: String, data: Bits*)(implicit sourceInfo: SourceInfo): Unit =