Module Hierarchy Refactor (#469)

1 files changed, 1 insertions, 1 deletions

diff --git a/chiselFrontend/src/main/scala/chisel3/core/Mem.scala b/chiselFrontend/src/main/scala/chisel3/core/Mem.scala
index a48af15a..006670e7 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Mem.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Mem.scala
@@ -95,7 +95,7 @@ sealed abstract class MemBase[T <: Data](t: T, val length: Int) extends HasId wi
        t.chiselCloneType, Node(this), dir, i.ref, Node(Builder.forcedClock))
     ).id
     // Bind each element of port to being a MemoryPort
-    Binding.bind(port, MemoryPortBinder(Builder.forcedModule), "Error: Fresh t")
+    Binding.bind(port, MemoryPortBinder(Builder.forcedUserModule), "Error: Fresh t")
     port
   }
 }