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| author | Jim Lawson | 2016-12-02 12:51:03 -0800 |
|---|---|---|
| committer | GitHub | 2016-12-02 12:51:03 -0800 |
| commit | d3ec37edd39799e8cf039e5caed915c00dff7eeb (patch) | |
| tree | 03329ddc11ca15b9d6c7f832354a9cba20c87843 /chiselFrontend/src/main/scala/chisel3/core/Mem.scala | |
| parent | 1b53d893816d349f5ea18fa0ed13325b9f1b6917 (diff) | |
| parent | eba224e524b249207b47a3b378458c61c9b66e2c (diff) | |
Merge branch 'master' into exceptionfix
Diffstat (limited to 'chiselFrontend/src/main/scala/chisel3/core/Mem.scala')
| -rw-r--r-- | chiselFrontend/src/main/scala/chisel3/core/Mem.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Mem.scala b/chiselFrontend/src/main/scala/chisel3/core/Mem.scala index a43b19fe..1863e921 100644 --- a/chiselFrontend/src/main/scala/chisel3/core/Mem.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/Mem.scala @@ -40,7 +40,7 @@ sealed abstract class MemBase[T <: Data](t: T, val length: Int) extends HasId wi */ def apply(idx: Int): T = { require(idx >= 0 && idx < length) - apply(UInt(idx)) + apply(idx.asUInt) } /** Creates a read/write accessor into the memory with dynamic addressing. |