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| author | Jim Lawson | 2016-12-12 09:14:33 -0800 |
|---|---|---|
| committer | GitHub | 2016-12-12 09:14:33 -0800 |
| commit | b581a24728bfba0c39ed2c032fd86f628a1e1a50 (patch) | |
| tree | f625219f936d39e760192aa69df17e776b95dd56 /chiselFrontend/src/main/scala/chisel3/core/Mem.scala | |
| parent | 0bd9ae059368570dc72f25f7939afa5cfe5fd06e (diff) | |
| parent | ad53161bbb9f67e16b88ca7a508a537f88d77e05 (diff) | |
Merge branch 'master' into buildinfousepackageaspath
Diffstat (limited to 'chiselFrontend/src/main/scala/chisel3/core/Mem.scala')
| -rw-r--r-- | chiselFrontend/src/main/scala/chisel3/core/Mem.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Mem.scala b/chiselFrontend/src/main/scala/chisel3/core/Mem.scala index a43b19fe..1863e921 100644 --- a/chiselFrontend/src/main/scala/chisel3/core/Mem.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/Mem.scala @@ -40,7 +40,7 @@ sealed abstract class MemBase[T <: Data](t: T, val length: Int) extends HasId wi */ def apply(idx: Int): T = { require(idx >= 0 && idx < length) - apply(UInt(idx)) + apply(idx.asUInt) } /** Creates a read/write accessor into the memory with dynamic addressing. |