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| author | Donggyu Kim | 2016-10-23 19:20:33 -0700 |
|---|---|---|
| committer | Donggyu Kim | 2016-10-23 19:20:33 -0700 |
| commit | aea7e1e754a3ebdb5b7e84c3ae1d35b16e547823 (patch) | |
| tree | 3c58fb89dec1cb93ccbc2f9404d757950a61d948 /chiselFrontend/src/main/scala/chisel3/core/Data.scala | |
| parent | bbc676b68a79ab2307d346c482d75b72f7ec5d4d (diff) | |
create SeqMems' read ports inside when statement
this helps firrtl to infer read enable signals
Diffstat (limited to 'chiselFrontend/src/main/scala/chisel3/core/Data.scala')
0 files changed, 0 insertions, 0 deletions