diff options
| author | Richard Lin | 2017-03-08 17:38:14 -0800 |
|---|---|---|
| committer | GitHub | 2017-03-08 17:38:14 -0800 |
| commit | a290d77ef3e88b200ab61cd41fcd1a1138321b66 (patch) | |
| tree | 3cbabf2a20dc34f9d60a585834f532070bcd5235 /chiselFrontend/src/main/scala/chisel3/core/Data.scala | |
| parent | 09e95c484e145e2a1b2f0a1aacf549c7354a1eca (diff) | |
Deprecate old Reg with nulls constructor (#455)
Diffstat (limited to 'chiselFrontend/src/main/scala/chisel3/core/Data.scala')
| -rw-r--r-- | chiselFrontend/src/main/scala/chisel3/core/Data.scala | 33 |
1 files changed, 21 insertions, 12 deletions
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Data.scala b/chiselFrontend/src/main/scala/chisel3/core/Data.scala index 410f498e..66720f7c 100644 --- a/chiselFrontend/src/main/scala/chisel3/core/Data.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/Data.scala @@ -334,28 +334,37 @@ abstract class Data extends HasId { } object Wire { - def apply[T <: Data](t: T): T = macro WireTransform.apply[T] - // No source info since Scala macros don't yet support named / default arguments. - def apply[T <: Data](dummy: Int = 0, init: T)(implicit compileOptions: CompileOptions): T = - do_apply(null.asInstanceOf[T], init)(UnlocatableSourceInfo, compileOptions) + def apply[T <: Data](dummy: Int = 0, init: T)(implicit compileOptions: CompileOptions): T = { + val model = (init.litArg match { + // For e.g. Wire(init=0.U(k.W)), fix the Reg's width to k + case Some(lit) if lit.forcedWidth => init.chiselCloneType + case _ => init match { + case init: Bits => init.cloneTypeWidth(Width()) + case init => init.chiselCloneType + } + }).asInstanceOf[T] + apply(model, init) + } // No source info since Scala macros don't yet support named / default arguments. - def apply[T <: Data](t: T, init: T)(implicit compileOptions: CompileOptions): T = - do_apply(t, init)(UnlocatableSourceInfo, compileOptions) + def apply[T <: Data](t: T, init: T)(implicit compileOptions: CompileOptions): T = { + implicit val noSourceInfo = UnlocatableSourceInfo + val x = apply(t) + Binding.checkSynthesizable(init, s"'init' ($init)") + x := init + x + } - def do_apply[T <: Data](t: T, init: T)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): T = { - val x = Reg.makeType(chisel3.core.ExplicitCompileOptions.NotStrict, t, null.asInstanceOf[T], init) + def apply[T <: Data](t: T)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): T = { + val x = t.chiselCloneType // Bind each element of x to being a Wire Binding.bind(x, WireBinder(Builder.forcedModule), "Error: t") pushCommand(DefWire(sourceInfo, x)) pushCommand(DefInvalid(sourceInfo, x.ref)) - if (init != null) { - Binding.checkSynthesizable(init, s"'init' ($init)") - x := init - } + x } } |
