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authorJack Koenig2019-05-09 18:35:10 -0500
committerAndrew Waterman2019-05-09 16:35:10 -0700
commit6be76f79f873873497e40fa647f9456391b4d59a (patch)
tree0660351d647f39baefa3b76180fd4dbb53d0285c /chiselFrontend/src/main/scala/chisel3/core/Data.scala
parenta9bf10cc40a5acf0f4bfb43744f9e12e8e1a0e25 (diff)
Fix treatment of Vec of Analog and Vec of Bundle of Analog (#1091)
* IO(Analog) fixed for RawModule * Add a Analog Port for RawModule test & spec * Fixes around Module instantiation and ports in AnalogPortRawModuleTest * Shorten Comment * Add Data.isSynthesizable to distinguish SampleElementBinding This helps clarify the notion of being bound but not hardware. Data.topBindingOpt is now used to get the *actual* top binding, including across SampleElements (eg. in Analog checking that the top is bound to a Port or a Wire) * Fix pretty printing for Vec * Refactor tests for Vec of Analog, add test for Vec of Bundle of Analog
Diffstat (limited to 'chiselFrontend/src/main/scala/chisel3/core/Data.scala')
-rw-r--r--chiselFrontend/src/main/scala/chisel3/core/Data.scala17
1 files changed, 11 insertions, 6 deletions
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Data.scala b/chiselFrontend/src/main/scala/chisel3/core/Data.scala
index abb5675c..7ff58b54 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Data.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Data.scala
@@ -146,7 +146,7 @@ object DataMirror {
// Internal reflection-style APIs, subject to change and removal whenever.
object internal { // scalastyle:ignore object.name
- def isSynthesizable(target: Data): Boolean = target.topBindingOpt.isDefined
+ def isSynthesizable(target: Data): Boolean = target.isSynthesizable
// For those odd cases where you need to care about object reference and uniqueness
def chiselTypeClone[T<:Data](target: Data): T = {
target.cloneTypeFull.asInstanceOf[T]
@@ -314,14 +314,18 @@ abstract class Data extends HasId with NamedComponent with SourceInfoDoc { // sc
_binding = Some(target)
}
+ // Similar to topBindingOpt except it explicitly excludes SampleElements which are bound but not
+ // hardware
+ private[core] final def isSynthesizable: Boolean = _binding.map {
+ case ChildBinding(parent) => parent.isSynthesizable
+ case _: TopBinding => true
+ case _: SampleElementBinding[_] => false
+ }.getOrElse(false)
+
private[core] def topBindingOpt: Option[TopBinding] = _binding.flatMap {
case ChildBinding(parent) => parent.topBindingOpt
case bindingVal: TopBinding => Some(bindingVal)
- case _: SampleElementBinding[_] => None
- // TODO: technically, it's bound, but it's more of a ghost binding and None is probably the most appropriate
- // Note: sample elements should not be user-accessible, so there's not really a good reason to access its
- // top binding. However, we can't make this assert out right not because a larger refactoring is needed.
- // See https://github.com/freechipsproject/chisel3/pull/946
+ case SampleElementBinding(parent) => parent.topBindingOpt
}
private[core] def topBinding: TopBinding = topBindingOpt.get
@@ -351,6 +355,7 @@ abstract class Data extends HasId with NamedComponent with SourceInfoDoc { // sc
// User-friendly representation of the binding as a helper function for toString.
// Provides a unhelpful fallback for literals, which should have custom rendering per
// Data-subtype.
+ // TODO Is this okay for sample_element? It *shouldn't* be visible to users
protected def bindingToString: String = topBindingOpt match {
case None => ""
case Some(OpBinding(enclosure)) => s"(OpResult in ${enclosure.desiredName})"