diff options
| author | Jim Lawson | 2016-09-29 11:44:09 -0700 |
|---|---|---|
| committer | Jim Lawson | 2016-09-29 11:44:09 -0700 |
| commit | eb5e5dc30019be342b7a0534b425bf33b7984ce3 (patch) | |
| tree | 1f04fd7157a17cc45fe1ff0835500d93809809fd /chiselFrontend/src/main/scala/chisel3/core/BlackBox.scala | |
| parent | 12a651513541d6c96e3b709b424d5d3384179076 (diff) | |
Massive rename of CompileOptions.
Massage CompileOption names in an attempt to preserve default (Strict) CompileOptions in the absence of explicit imports.
NOTE: Since the default is now strict, we may encounter errors when we generate connections for clients (i.e., in Vec.do_apply() when we wire up a sequence).
We should really thread the CompileOptions through the macro system so the client's implicits are used.
Diffstat (limited to 'chiselFrontend/src/main/scala/chisel3/core/BlackBox.scala')
| -rw-r--r-- | chiselFrontend/src/main/scala/chisel3/core/BlackBox.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/chiselFrontend/src/main/scala/chisel3/core/BlackBox.scala b/chiselFrontend/src/main/scala/chisel3/core/BlackBox.scala index 7b0cf3f7..7e61ec72 100644 --- a/chiselFrontend/src/main/scala/chisel3/core/BlackBox.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/BlackBox.scala @@ -5,7 +5,7 @@ package chisel3.core import chisel3.internal.Builder.pushCommand import chisel3.internal.firrtl.{ModuleIO, DefInvalid} import chisel3.internal.sourceinfo.SourceInfo -import chisel3.NotStrict.CompileOptions +//import chisel3.ExplicitCompileOptions.NotStrict /** Defines a black box, which is a module that can be referenced from within * Chisel, but is not defined in the emitted Verilog. Useful for connecting |