diff options
| author | Jim Lawson | 2016-09-30 12:13:58 -0700 |
|---|---|---|
| committer | GitHub | 2016-09-30 12:13:58 -0700 |
| commit | db25e8180a53fb8f4912fd37b7a613e15a01564f (patch) | |
| tree | 8bb5597746002ac98641f394cee4c94e1d154aff /chiselFrontend/src/main/scala/chisel3/core/BlackBox.scala | |
| parent | 785620b1403d827986bf60c2a001d8d6f71eed72 (diff) | |
| parent | 6edbdf279257d656b5eac38d9de8645a068611bf (diff) | |
Merge pull request #265 from ucb-bar/gsdt
Gsdt - Fixup to Chisel connections and direction - PR 200 revisited.
Diffstat (limited to 'chiselFrontend/src/main/scala/chisel3/core/BlackBox.scala')
| -rw-r--r-- | chiselFrontend/src/main/scala/chisel3/core/BlackBox.scala | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/chiselFrontend/src/main/scala/chisel3/core/BlackBox.scala b/chiselFrontend/src/main/scala/chisel3/core/BlackBox.scala index f2d9558d..c1352566 100644 --- a/chiselFrontend/src/main/scala/chisel3/core/BlackBox.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/BlackBox.scala @@ -5,6 +5,8 @@ package chisel3.core import chisel3.internal.Builder.pushCommand import chisel3.internal.firrtl.{ModuleIO, DefInvalid} import chisel3.internal.sourceinfo.SourceInfo +// TODO: remove this once we have CompileOptions threaded through the macro system. +import chisel3.core.ExplicitCompileOptions.NotStrict /** Defines a black box, which is a module that can be referenced from within * Chisel, but is not defined in the emitted Verilog. Useful for connecting |