diff options
| author | Richard Lin | 2018-10-03 16:15:37 -0700 |
|---|---|---|
| committer | GitHub | 2018-10-03 16:15:37 -0700 |
| commit | dafdeab614a5106dac4d80e147fdbc2770053e1b (patch) | |
| tree | efd4ae2f9b612e55c87227851813afb6644ddd3a /chiselFrontend/src/main/scala/chisel3/core/BlackBox.scala | |
| parent | b87e6cf65920832c5a0d908b9862edcccf5cae5d (diff) | |
Add DataMirror.modulePorts (#901)
Diffstat (limited to 'chiselFrontend/src/main/scala/chisel3/core/BlackBox.scala')
| -rw-r--r-- | chiselFrontend/src/main/scala/chisel3/core/BlackBox.scala | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/chiselFrontend/src/main/scala/chisel3/core/BlackBox.scala b/chiselFrontend/src/main/scala/chisel3/core/BlackBox.scala index 3e7251c5..57acd7b3 100644 --- a/chiselFrontend/src/main/scala/chisel3/core/BlackBox.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/BlackBox.scala @@ -140,7 +140,8 @@ abstract class BlackBox(val params: Map[String, Param] = Map.empty[String, Param require(!_closed, "Can't generate module more than once") _closed = true - val namedPorts = io.elements.toSeq + val namedPorts = io.elements.toSeq.reverse // ListMaps are stored in reverse order + // setRef is not called on the actual io. // There is a risk of user improperly attempting to connect directly with io // Long term solution will be to define BlackBox IO differently as part of |