diff options
| author | Richard Lin | 2017-04-13 22:59:00 -0700 |
|---|---|---|
| committer | GitHub | 2017-04-13 22:59:00 -0700 |
| commit | e07248b8f6022fafdb84f5d1c0ebe3fc90a5475a (patch) | |
| tree | f2bb938fd35651b4fc7b88cbcd20e163cc75dd2e /chiselFrontend/src/main/scala/chisel3/core/Bits.scala | |
| parent | 97902cdc53eec52aa0cd806b8cb49a0e3f2fb769 (diff) | |
Module Hierarchy Refactor (#469)
Diffstat (limited to 'chiselFrontend/src/main/scala/chisel3/core/Bits.scala')
| -rw-r--r-- | chiselFrontend/src/main/scala/chisel3/core/Bits.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Bits.scala b/chiselFrontend/src/main/scala/chisel3/core/Bits.scala index dd3a2e8b..a8a96946 100644 --- a/chiselFrontend/src/main/scala/chisel3/core/Bits.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/Bits.scala @@ -1047,7 +1047,7 @@ final class Analog private (width: Width) extends Element(width) { // Used to enforce single bulk connect of Analog types, multi-attach is still okay // Note that this really means 1 bulk connect per Module because a port can // be connected in the parent module as well - private[core] val biConnectLocs = mutable.Map.empty[Module, SourceInfo] + private[core] val biConnectLocs = mutable.Map.empty[UserModule, SourceInfo] // Define setter/getter pairing // Analog can only be bound to Ports and Wires (and Unbound) |