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authorducky2018-06-28 17:34:05 -0700
committerRichard Lin2018-07-04 18:39:28 -0500
commita931abe0cf57481b47093b5950d3bffd9575f803 (patch)
tree90b26b281a03924bc7065d8670565019d2d77de7 /chiselFrontend/src/main/scala/chisel3/core/Bits.scala
parent6d3ed38e71b5f2a50dd1d424172f8ef6859a0e3d (diff)
Change [public] Data.elementLitArg => [protected] Aggregate.litArgOfBits
Diffstat (limited to 'chiselFrontend/src/main/scala/chisel3/core/Bits.scala')
-rw-r--r--chiselFrontend/src/main/scala/chisel3/core/Bits.scala6
1 files changed, 2 insertions, 4 deletions
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Bits.scala b/chiselFrontend/src/main/scala/chisel3/core/Bits.scala
index d39cc088..a8ebab1b 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Bits.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Bits.scala
@@ -81,15 +81,13 @@ sealed abstract class Bits(width: Width)
case topBindingOpt => topBindingOpt
}
- protected def litArgOption: Option[LitArg] = topBindingOpt match {
+ private[core] def litArgOption: Option[LitArg] = topBindingOpt match {
case Some(ElementLitBinding(litArg)) => Some(litArg)
case _ => None
}
override def litToBigIntOption: Option[BigInt] = litArgOption.map(_.num)
- private[chisel3] def litIsForcedWidth: Option[Boolean] = litArgOption.map(_.forcedWidth)
-
- override def elementLitArg: Option[LitArg] = litArgOption
+ private[core] def litIsForcedWidth: Option[Boolean] = litArgOption.map(_.forcedWidth)
// provide bits-specific literal handling functionality here
override private[chisel3] def ref: Arg = topBindingOpt match {