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| author | Richard Lin | 2019-01-21 16:24:43 -0800 |
|---|---|---|
| committer | GitHub | 2019-01-21 16:24:43 -0800 |
| commit | 9e992816e570284193e121cd9c24503fd8cb4427 (patch) | |
| tree | 90205ab0c936d50f4853bb7dc6293a4b62d47edf /chiselFrontend/src/main/scala/chisel3/core/Bits.scala | |
| parent | 3b3405e8bd496749dcb47e17156c0224a6f8a496 (diff) | |
Unify internal (chisel3.core) and external (chisel3 / chisel3.experimental) Module class names (#994)
Diffstat (limited to 'chiselFrontend/src/main/scala/chisel3/core/Bits.scala')
| -rw-r--r-- | chiselFrontend/src/main/scala/chisel3/core/Bits.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Bits.scala b/chiselFrontend/src/main/scala/chisel3/core/Bits.scala index abc7b583..83c8637a 100644 --- a/chiselFrontend/src/main/scala/chisel3/core/Bits.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/Bits.scala @@ -1734,7 +1734,7 @@ final class Analog private (private[chisel3] val width: Width) extends Element { // Used to enforce single bulk connect of Analog types, multi-attach is still okay // Note that this really means 1 bulk connect per Module because a port can // be connected in the parent module as well - private[core] val biConnectLocs = mutable.Map.empty[UserModule, SourceInfo] + private[core] val biConnectLocs = mutable.Map.empty[RawModule, SourceInfo] // Define setter/getter pairing // Analog can only be bound to Ports and Wires (and Unbound) |