diff options
| author | Jack Koenig | 2019-05-09 18:35:10 -0500 |
|---|---|---|
| committer | Andrew Waterman | 2019-05-09 16:35:10 -0700 |
| commit | 6be76f79f873873497e40fa647f9456391b4d59a (patch) | |
| tree | 0660351d647f39baefa3b76180fd4dbb53d0285c /chiselFrontend/src/main/scala/chisel3/core/Bits.scala | |
| parent | a9bf10cc40a5acf0f4bfb43744f9e12e8e1a0e25 (diff) | |
Fix treatment of Vec of Analog and Vec of Bundle of Analog (#1091)
* IO(Analog) fixed for RawModule
* Add a Analog Port for RawModule test & spec
* Fixes around Module instantiation and ports in AnalogPortRawModuleTest
* Shorten Comment
* Add Data.isSynthesizable to distinguish SampleElementBinding
This helps clarify the notion of being bound but not hardware.
Data.topBindingOpt is now used to get the *actual* top binding,
including across SampleElements (eg. in Analog checking that the top is
bound to a Port or a Wire)
* Fix pretty printing for Vec
* Refactor tests for Vec of Analog, add test for Vec of Bundle of Analog
Diffstat (limited to 'chiselFrontend/src/main/scala/chisel3/core/Bits.scala')
| -rw-r--r-- | chiselFrontend/src/main/scala/chisel3/core/Bits.scala | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Bits.scala b/chiselFrontend/src/main/scala/chisel3/core/Bits.scala index e35d12f0..424db5cb 100644 --- a/chiselFrontend/src/main/scala/chisel3/core/Bits.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/Bits.scala @@ -1776,6 +1776,8 @@ final class Analog private (private[chisel3] val width: Width) extends Element { val targetTopBinding = target match { case target: TopBinding => target case ChildBinding(parent) => parent.topBinding + // See https://github.com/freechipsproject/chisel3/pull/946 + case SampleElementBinding(parent) => parent.topBinding } // Analog counts as different directions based on binding context |