diff options
| author | Andrew Waterman | 2016-08-31 19:23:11 -0700 |
|---|---|---|
| committer | Andrew Waterman | 2016-08-31 19:23:58 -0700 |
| commit | 3442fac58a99551ca9e25dbc2c363c866c40e3cf (patch) | |
| tree | 2f5b74bb83c3e2caba64cb42dc90c6e88b7408c9 /chiselFrontend/src/main/scala/chisel3/core/Bits.scala | |
| parent | e2c76e1b752cb332d6c3b23dd224db14951c7e72 (diff) | |
Check that Vecs have homogeneous types
Vec[Element] can have heterogeneous widths.
Vec[Aggregate] cannot (but possibly could relax this by stripping widths
from constituent Elements and relying on width inference).
Diffstat (limited to 'chiselFrontend/src/main/scala/chisel3/core/Bits.scala')
| -rw-r--r-- | chiselFrontend/src/main/scala/chisel3/core/Bits.scala | 11 |
1 files changed, 8 insertions, 3 deletions
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Bits.scala b/chiselFrontend/src/main/scala/chisel3/core/Bits.scala index 015b9dfb..44beab66 100644 --- a/chiselFrontend/src/main/scala/chisel3/core/Bits.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/Bits.scala @@ -737,10 +737,15 @@ object Mux { pushOp(DefPrim(sourceInfo, d, MultiplexOp, cond.ref, con.ref, alt.ref)) } + private[core] def typesCompatible[T <: Data](x: T, y: T): Boolean = { + val sameTypes = x.getClass == y.getClass + val sameElements = x.flatten zip y.flatten forall { case (a, b) => a.getClass == b.getClass && a.width == b.width } + val sameNumElements = x.flatten.size == y.flatten.size + sameTypes && sameElements && sameNumElements + } + private def doAggregateMux[T <: Data](cond: Bool, con: T, alt: T)(implicit sourceInfo: SourceInfo): T = { - require(con.getClass == alt.getClass, s"can't Mux between ${con.getClass} and ${alt.getClass}") - for ((c, a) <- con.flatten zip alt.flatten) - require(c.width == a.width, "can't Mux between aggregates of different width") + require(typesCompatible(con, alt), s"can't Mux between heterogeneous types ${con.getClass} and ${alt.getClass}") doMux(cond, con, alt) } } |
