diff options
| author | Richard Lin | 2017-04-13 22:59:00 -0700 |
|---|---|---|
| committer | GitHub | 2017-04-13 22:59:00 -0700 |
| commit | e07248b8f6022fafdb84f5d1c0ebe3fc90a5475a (patch) | |
| tree | f2bb938fd35651b4fc7b88cbcd20e163cc75dd2e /chiselFrontend/src/main/scala/chisel3/core/BiConnect.scala | |
| parent | 97902cdc53eec52aa0cd806b8cb49a0e3f2fb769 (diff) | |
Module Hierarchy Refactor (#469)
Diffstat (limited to 'chiselFrontend/src/main/scala/chisel3/core/BiConnect.scala')
| -rw-r--r-- | chiselFrontend/src/main/scala/chisel3/core/BiConnect.scala | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/chiselFrontend/src/main/scala/chisel3/core/BiConnect.scala b/chiselFrontend/src/main/scala/chisel3/core/BiConnect.scala index 825dbad7..95ad95ef 100644 --- a/chiselFrontend/src/main/scala/chisel3/core/BiConnect.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/BiConnect.scala @@ -54,7 +54,7 @@ object BiConnect { * during the recursive decent and then rethrow them with extra information added. * This gives the user a 'path' to where in the connections things went wrong. */ - def connect(sourceInfo: SourceInfo, connectCompileOptions: CompileOptions, left: Data, right: Data, context_mod: Module): Unit = + def connect(sourceInfo: SourceInfo, connectCompileOptions: CompileOptions, left: Data, right: Data, context_mod: UserModule): Unit = (left, right) match { // Handle element case (root case) case (left_a: Analog, right_a: Analog) => @@ -121,12 +121,12 @@ object BiConnect { // This function checks if element-level connection operation allowed. // Then it either issues it or throws the appropriate exception. - def elemConnect(implicit sourceInfo: SourceInfo, connectCompileOptions: CompileOptions, left: Element, right: Element, context_mod: Module): Unit = { + def elemConnect(implicit sourceInfo: SourceInfo, connectCompileOptions: CompileOptions, left: Element, right: Element, context_mod: UserModule): Unit = { import Direction.{Input, Output} // Using extensively so import these // If left or right have no location, assume in context module // This can occur if one of them is a literal, unbound will error previously - val left_mod: Module = left.binding.location.getOrElse(context_mod) - val right_mod: Module = right.binding.location.getOrElse(context_mod) + val left_mod: BaseModule = left.binding.location.getOrElse(context_mod) + val right_mod: BaseModule = right.binding.location.getOrElse(context_mod) val left_direction: Option[Direction] = left.binding.direction val right_direction: Option[Direction] = right.binding.direction @@ -250,7 +250,7 @@ object BiConnect { // This function checks if analog element-level attaching is allowed // Then it either issues it or throws the appropriate exception. - def analogAttach(implicit sourceInfo: SourceInfo, left: Analog, right: Analog, contextModule: Module): Unit = { + def analogAttach(implicit sourceInfo: SourceInfo, left: Analog, right: Analog, contextModule: UserModule): Unit = { // Error if left or right is BICONNECTED in the current module already for (elt <- left :: right :: Nil) { elt.biConnectLocs.get(contextModule) match { |
