Trim Stack Trace (#931)

- Trim stack trace to show better, reduced information to the user
- Add --full-stacktrace to FIRRTL option to show full stack trace

1 files changed, 2 insertions, 1 deletions

diff --git a/chiselFrontend/src/main/scala/chisel3/core/BiConnect.scala b/chiselFrontend/src/main/scala/chisel3/core/BiConnect.scala
index 1dcb968d..ad7ba98a 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/BiConnect.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/BiConnect.scala
@@ -2,6 +2,7 @@
 
 package chisel3.core
 
+import chisel3.internal.ChiselException
 import chisel3.internal.Builder.pushCommand
 import chisel3.internal.firrtl.{Connect, DefInvalid}
 import scala.language.experimental.macros
@@ -23,7 +24,7 @@ import chisel3.internal.sourceinfo._
 
 object BiConnect {
   // These are all the possible exceptions that can be thrown.
-  case class BiConnectException(message: String) extends Exception(message)
+  case class BiConnectException(message: String) extends ChiselException(message)
   // These are from element-level connection
   def BothDriversException =
     BiConnectException(": Both Left and Right are drivers")