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authorRichard Lin2019-01-21 16:24:43 -0800
committerGitHub2019-01-21 16:24:43 -0800
commit9e992816e570284193e121cd9c24503fd8cb4427 (patch)
tree90205ab0c936d50f4853bb7dc6293a4b62d47edf /chiselFrontend/src/main/scala/chisel3/core/BiConnect.scala
parent3b3405e8bd496749dcb47e17156c0224a6f8a496 (diff)
Unify internal (chisel3.core) and external (chisel3 / chisel3.experimental) Module class names (#994)
Diffstat (limited to 'chiselFrontend/src/main/scala/chisel3/core/BiConnect.scala')
-rw-r--r--chiselFrontend/src/main/scala/chisel3/core/BiConnect.scala8
1 files changed, 4 insertions, 4 deletions
diff --git a/chiselFrontend/src/main/scala/chisel3/core/BiConnect.scala b/chiselFrontend/src/main/scala/chisel3/core/BiConnect.scala
index ad7ba98a..897ccacf 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/BiConnect.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/BiConnect.scala
@@ -55,7 +55,7 @@ object BiConnect {
* during the recursive decent and then rethrow them with extra information added.
* This gives the user a 'path' to where in the connections things went wrong.
*/
- def connect(sourceInfo: SourceInfo, connectCompileOptions: CompileOptions, left: Data, right: Data, context_mod: UserModule): Unit = {
+ def connect(sourceInfo: SourceInfo, connectCompileOptions: CompileOptions, left: Data, right: Data, context_mod: RawModule): Unit = {
(left, right) match {
// Handle element case (root case)
case (left_a: Analog, right_a: Analog) =>
@@ -154,7 +154,7 @@ object BiConnect {
connectCompileOptions: CompileOptions,
left_r: Record,
right_r: Record,
- context_mod: UserModule): Unit = {
+ context_mod: RawModule): Unit = {
// Verify right has no extra fields that left doesn't have
for((field, right_sub) <- right_r.elements) {
if(!left_r.elements.isDefinedAt(field)) {
@@ -207,7 +207,7 @@ object BiConnect {
// This function checks if element-level connection operation allowed.
// Then it either issues it or throws the appropriate exception.
- def elemConnect(implicit sourceInfo: SourceInfo, connectCompileOptions: CompileOptions, left: Element, right: Element, context_mod: UserModule): Unit = {
+ def elemConnect(implicit sourceInfo: SourceInfo, connectCompileOptions: CompileOptions, left: Element, right: Element, context_mod: RawModule): Unit = {
import BindingDirection.{Internal, Input, Output} // Using extensively so import these
// If left or right have no location, assume in context module
// This can occur if one of them is a literal, unbound will error previously
@@ -313,7 +313,7 @@ object BiConnect {
// This function checks if analog element-level attaching is allowed
// Then it either issues it or throws the appropriate exception.
- def analogAttach(implicit sourceInfo: SourceInfo, left: Analog, right: Analog, contextModule: UserModule): Unit = {
+ def analogAttach(implicit sourceInfo: SourceInfo, left: Analog, right: Analog, contextModule: RawModule): Unit = {
// Error if left or right is BICONNECTED in the current module already
for (elt <- left :: right :: Nil) {
elt.biConnectLocs.get(contextModule) match {