Add Analog type

Used for stitching Verilog inout through Chisel Modules (from BlackBox
to BlackBox)

1 files changed, 45 insertions, 0 deletions

diff --git a/chiselFrontend/src/main/scala/chisel3/core/Attach.scala b/chiselFrontend/src/main/scala/chisel3/core/Attach.scala
new file mode 100644
index 00000000..5e767b84
--- /dev/null
+++ b/chiselFrontend/src/main/scala/chisel3/core/Attach.scala
@@ -0,0 +1,45 @@
+// See LICENSE for license details.
+
+package chisel3.core
+
+import chisel3.internal._
+import chisel3.internal.Builder.pushCommand
+import chisel3.internal.firrtl._
+import chisel3.internal.sourceinfo.{SourceInfo}
+
+object attach {  // scalastyle:ignore object.name
+  // Exceptions that can be generated by attach
+  case class AttachException(message: String) extends Exception(message)
+  def ConditionalAttachException =
+    AttachException(": Conditional attach is not allowed!")
+
+  // Actual implementation
+  private[core] def impl(elts: Seq[Analog], contextModule: Module)(implicit sourceInfo: SourceInfo): Unit = {
+    if (Builder.whenDepth != 0) throw ConditionalAttachException
+
+    // TODO Check that references are valid and can be attached
+
+    pushCommand(Attach(sourceInfo, elts.map(_.lref)))
+  }
+
+  /** Create an electrical connection between [[Analog]] components
+    *
+    * @param elts The components to attach
+    *
+    * @example
+    * {{{
+    * val a1 = Wire(Analog(32.W))
+    * val a2 = Wire(Analog(32.W))
+    * attach(a1, a2)
+    * }}}
+    */
+  def apply(elts: Analog*)(implicit sourceInfo: SourceInfo): Unit = {
+    try {
+      impl(elts, Builder.forcedModule)
+    } catch {
+      case AttachException(message) =>
+        throwException(elts.mkString("Attaching (", ", ", s") failed @$message"))
+    }
+  }
+}
+