Merge pull request #1022 from freechipsproject/cleanup-scaladoc

Miscellaneous Scaladoc Cleanup

1 files changed, 5 insertions, 5 deletions

diff --git a/chiselFrontend/src/main/scala/chisel3/core/Annotation.scala b/chiselFrontend/src/main/scala/chisel3/core/Annotation.scala
index b2c9ea78..b7e82f63 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Annotation.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Annotation.scala
@@ -5,7 +5,6 @@ package chisel3.core
 import scala.language.existentials
 
 import chisel3.internal.{Builder, InstanceId}
-import chisel3.core.ImplicitModule
 import firrtl.Transform
 import firrtl.annotations.{Annotation, CircuitName, ComponentName, ModuleName}
 import firrtl.transforms.{DontTouchAnnotation, NoDedupAnnotation}
@@ -30,9 +29,10 @@ object ChiselAnnotation {
     }
 }
 
-/** Mixin for [[ChiselAnnotation]] that instantiates an associated FIRRTL Transform when this
-  * Annotation is present during a run of [[chisel3.Driver.execute]]. Automatic Transform
-  * instantiation is *not* supported when the Circuit and Annotations are serialized before invoking
+/** Mixin for [[ChiselAnnotation]] that instantiates an associated FIRRTL Transform when this Annotation is present
+  * during a run of
+  * [[Driver$.execute(args:Array[String],dut:()=>chisel3\.experimental\.RawModule)* Driver.execute]].
+  * Automatic Transform instantiation is *not* supported when the Circuit and Annotations are serialized before invoking
   * FIRRTL.
   */
 // TODO There should be a FIRRTL API for this instead
@@ -99,7 +99,7 @@ object dontTouch { // scalastyle:ignore object.name
   *        val b = Input(UInt(32.W))
   *        val out = Output(UInt(32.W))
   *      })
-  *      override def desiredName = s"adder_$myNname"
+  *      override def desiredName = "adder_" + myNname
   *      io.out := io.a + io.b
   *    })
   *    doNotDedup(m)