diff options
| author | grebe | 2017-01-13 09:51:18 -0800 |
|---|---|---|
| committer | Chick Markley | 2017-01-13 09:51:18 -0800 |
| commit | f19653fbe9d2e1b49c49c31ddb98a758c390ba94 (patch) | |
| tree | cd295142ab5a0040c4beb5606fc1c2cdc2901e28 /chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala | |
| parent | 3215df07a97b58babb1deb3fab0928198b1daad2 (diff) | |
Make fromBits work with types other than UInt (#424)
* Make fromBits work with types other than UInt
* Oops, left in a println
* Add test for truncation/expansion
* Fix stuff that broke when FixedPoint fromBits PR was merged.
* Use .BP shorthand added in previous PR
Diffstat (limited to 'chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala')
| -rw-r--r-- | chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala b/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala index 26c971b3..559a55bc 100644 --- a/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala @@ -21,6 +21,21 @@ sealed abstract class Aggregate extends Data { pushCommand(BulkConnect(sourceInfo, this.lref, that.lref)) override def do_asUInt(implicit sourceInfo: SourceInfo): UInt = SeqUtils.do_asUInt(this.flatten) + def do_fromBits(that: Bits)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): this.type = { + var i = 0 + val wire = Wire(this.chiselCloneType) + val bits = + if (that.width.known && that.width.get >= wire.width.get) { + that + } else { + Wire(that.cloneTypeWidth(wire.width), init = that) + } + for (x <- wire.flatten) { + x := x.fromBits(bits(i + x.getWidth-1, i)) + i += x.getWidth + } + wire.asInstanceOf[this.type] + } } object Vec { |
