diff options
| author | Adam Izraelevitz | 2017-10-26 12:39:42 -0700 |
|---|---|---|
| committer | Jim Lawson | 2017-10-26 12:39:42 -0700 |
| commit | c313e137d4e562ef20195312501840ceab8cbc6a (patch) | |
| tree | 37e290d3c5af672624b9ac267ccb33421acca84e /chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala | |
| parent | 8168a8eea6c3465966081c5acd0347e09791361c (diff) | |
Invalidateapi (#645)
* Require explicit connection to DontCare to generate "is invalid".
* Add tests for RefNotInitializedException.
Currently, we fail the when ... otherwise ...
* Disable ScalaTest shrinking on error in ComplexAssignSpec.
* fix broken merge; still some binding issues
* cleanup DontCare connection checks; add missing directions to test module IOs
* Have library code inherit compileOptions from the enclosing Module (if it exists).
* work around current firrtl uninitialized references with Strict compile options and explicitInvalidate
* more CompileOptions cleanup; move test-specific defines to package object
* minimize differences with master
* set default CompileOptions.explicitInvalidate to false until we fix the FIRRTL when issue
* ignore the StrictCompiler property checks (until CompileOptions.explicitInvalidate is defaulted to true)
* Revert "more CompileOptions cleanup; move test-specific defines to package object"
This reverts commit e4486edcba990d150e76e08a2fc6abca033556e0.
* Revert "work around current firrtl uninitialized references with Strict compile options and explicitInvalidate"
This reverts commit 426faa430a62c3dac2dbdf33044d3386d4243157.
* remove unused code
* Convert to binding-based DontCare implementation
* comment cleanup to minimize differences with master
* Tentatively remove possibly redundant DefInvalid on module ports.
* Respond to code review change request.
- backout build.sbt change
- correct indentation
- handle bulk of DontCare semantics in elemConnect()
- have DontCare extend Element, not Data (eliminate most Object specific methods
- add comments indicating reason for explicit DontCare connections
* Initialize test elements without requiring a DontCare.
* Respond to review change requests.
- DontCare should work on left or right side in BiDirectional connections
- call bind() to set DontCare binding instead of messing with internal variables
- DontCares are only equivalent with DontCares
- clean up processWhens() definition
* Eliminate DontCare connection to inputs in MonoConnect().
* Pull aggregates apart for the purpose of DontCare connections.
* Restore the explicit (conditionally executed) ports DefInvalidin ImplicitModule()
* Don't add DontCare's to the module list of _ids.
* Add missing DefInvalid() to LegacyModule().
* Respond to review requests: add DontCare BiConnect Vec, remove null parent hack to avoid addId(), initialize singletons early in Builder
* Move DontCare out of chisel3.experimental.
Diffstat (limited to 'chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala')
| -rw-r--r-- | chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala | 11 |
1 files changed, 9 insertions, 2 deletions
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala b/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala index 47f4b3e7..88cc6ff6 100644 --- a/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala @@ -67,8 +67,15 @@ sealed abstract class Aggregate extends Data { def getElements: Seq[Data] private[chisel3] def width: Width = getElements.map(_.width).foldLeft(0.W)(_ + _) - private[core] def legacyConnect(that: Data)(implicit sourceInfo: SourceInfo): Unit = - pushCommand(BulkConnect(sourceInfo, this.lref, that.lref)) + private[core] def legacyConnect(that: Data)(implicit sourceInfo: SourceInfo): Unit = { + // If the source is a DontCare, generate a DefInvalid for the sink, + // otherwise, issue a Connect. + if (that == DontCare) { + pushCommand(DefInvalid(sourceInfo, this.lref)) + } else { + pushCommand(BulkConnect(sourceInfo, this.lref, that.lref)) + } + } override def do_asUInt(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): UInt = { SeqUtils.do_asUInt(flatten.map(_.asUInt())) |
